Unverified Commit 50e7592c authored by Hsin-Te Yuan's avatar Hsin-Te Yuan Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM cells 



On the MT8188, the chip is binned for different GPU voltages at the
highest OPPs. The binning value is stored in the efuse.

Add the NVMEM cell, and tie it to the GPU.

Signed-off-by: default avatarHsin-Te Yuan <yuanhsinte@chromium.org>
Link: https://lore.kernel.org/r/20241213-speedbin-v1-1-a0053ead9477@chromium.org


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 95949352

arch/arm64/boot/dts/mediatek/mt8188.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -2125,6 +2125,11 @@ lvts_efuse_data1: lvts1-calib@1ac { 
				reg = <0x1ac 0x40>;

			};



			gpu_speedbin: gpu-speedbin@581 {

				reg = <0x581 0x1>;

				bits = <0 3>;

			};



			socinfo-data1@7a0 {

				reg = <0x7a0 0x4>;

			};
@@ -2143,6 +2148,8 @@ gpu: gpu@13000000 { 
				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,

				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;

			interrupt-names = "job", "mmu", "gpu";

			nvmem-cells = <&gpu_speedbin>;

			nvmem-cell-names = "speed-bin";

			operating-points-v2 = <&gpu_opp_table>;

			power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,

					<&spm MT8188_POWER_DOMAIN_MFG3>,