Commit 50f040c5 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Increase halt timeout for DMCUB to 1s 



[Why]
If we soft reset before halt finishes and there are outstanding
memory transactions then the memory interface may produce unexpected
results, such as out of order transactions when the firmware next runs.

These can manifest as random or unexpected load/store violations.

[How]
Increase the timeout before soft reset to ensure the DMCUB has quiesced.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35079e7e

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+10 −5
Original line number Diff line number Diff line
@@ -83,8 +83,8 @@ static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in, 
void dmub_dcn31_reset(struct dmub_srv *dmub)

{

	union dmub_gpint_data_register cmd;

	const uint32_t timeout = 100;

	uint32_t in_reset, scratch, i, pwait_mode;

	const uint32_t timeout = 1000000;

	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;



	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
@@ -125,9 +125,14 @@ void dmub_dcn31_reset(struct dmub_srv *dmub) 
		/* Force reset in case we timed out, DMCUB is likely hung. */

	}



	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled);



	if (is_enabled) {

		REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);

	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

		REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);

		REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

	}



	REG_WRITE(DMCUB_INBOX1_RPTR, 0);

	REG_WRITE(DMCUB_INBOX1_WPTR, 0);

	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

+1 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in, 
void dmub_dcn35_reset(struct dmub_srv *dmub)

{

	union dmub_gpint_data_register cmd;

	const uint32_t timeout = 100;

	const uint32_t timeout = 1000000;

	uint32_t in_reset, is_enabled, scratch, i, pwait_mode;



	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);