Commit 5120243b authored by Vitaly Lubart's avatar Vitaly Lubart Committed by Rodrigo Vivi
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drm/xe/gsc: add HECI2 register offsets 



Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarVitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent cd0adf74

drivers/gpu/drm/xe/regs/xe_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -33,6 +33,10 @@ 
#define XEHPC_BCS6_RING_BASE			0x3ea000

#define XEHPC_BCS7_RING_BASE			0x3ec000

#define XEHPC_BCS8_RING_BASE			0x3ee000



#define DG1_GSC_HECI2_BASE                      0x00259000

#define DG2_GSC_HECI2_BASE                      0x00374000



#define GSCCS_RING_BASE				0x11a000

#define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)

#define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)