Commit 512b322b authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

drm/amd/pm: support pp_dpm_pcie on smu v14.0.2/3 



support pp_dpm_pcie on smu v14.0.2/3

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarJack Gui <Jack.Gui@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d3620eea

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

+6 −0
Original line number Diff line number Diff line
@@ -48,6 +48,12 @@ 


#define SMU14_TOOL_SIZE			0x19000



extern const int decoded_link_speed[5];

extern const int decoded_link_width[7];



#define DECODE_GEN_SPEED(gen_speed_idx)		(decoded_link_speed[gen_speed_idx])

#define DECODE_LANE_WIDTH(lane_width_idx)	(decoded_link_width[lane_width_idx])



struct smu_14_0_max_sustainable_clocks {

	uint32_t display_clock;

	uint32_t phy_clock;

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0            0x0342

#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX   0



const int decoded_link_speed[5] = {1, 2, 3, 4, 5};

const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};

/*

 * DO NOT use these for err/warn/info/debug messages.

 * Use dev_err, dev_warn, dev_info and dev_dbg instead.

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

+31 −1
Original line number Diff line number Diff line
@@ -1036,6 +1036,8 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, 
	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context;

	struct smu_14_0_dpm_table *single_dpm_table;

	struct smu_14_0_pcie_table *pcie_table;

	uint32_t gen_speed, lane_width;

	int i, curr_freq, size = 0;

	int ret = 0;
@@ -1126,7 +1128,35 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, 
		}

		break;

	case SMU_PCIE:

		// TODO

		ret = smu_v14_0_2_get_smu_metrics_data(smu,

						       METRICS_PCIE_RATE,

						       &gen_speed);

		if (ret)

			return ret;



		ret = smu_v14_0_2_get_smu_metrics_data(smu,

						       METRICS_PCIE_WIDTH,

						       &lane_width);

		if (ret)

			return ret;



		pcie_table = &(dpm_context->dpm_tables.pcie_table);

		for (i = 0; i < pcie_table->num_of_link_levels; i++)

			size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,

					(pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :

					(pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :

					(pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :

					(pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",

					(pcie_table->pcie_lane[i] == 1) ? "x1" :

					(pcie_table->pcie_lane[i] == 2) ? "x2" :

					(pcie_table->pcie_lane[i] == 3) ? "x4" :

					(pcie_table->pcie_lane[i] == 4) ? "x8" :

					(pcie_table->pcie_lane[i] == 5) ? "x12" :

					(pcie_table->pcie_lane[i] == 6) ? "x16" : "",

					pcie_table->clk_freq[i],

					(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&

					(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?

					"*" : "");

		break;



	default: