Unverified Commit 5151fa35 authored by Juha-Pekka Heikkila's avatar Juha-Pekka Heikkila Committed by Rodrigo Vivi
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drm/fourcc: define Intel Xe2 related tile4 ccs modifiers 



Add Tile4 type ccs modifiers to indicate presence of compression on Xe2.
Here is defined I915_FORMAT_MOD_4_TILED_LNL_CCS which is meant for
integrated graphics with igpu related limitations
Here is also defined I915_FORMAT_MOD_4_TILED_BMG_CCS which is meant
for discrete graphics with dgpu related limitations

Signed-off-by: default avatarJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-3-juhapekka.heikkila@gmail.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 4cce34b3

include/uapi/drm/drm_fourcc.h

+25 −0
Original line number Diff line number Diff line
@@ -702,6 +702,31 @@ extern "C" { 
 */

#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)



/*

 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression

 * on integrated graphics

 *

 * The main surface is Tile 4 and at plane index 0. For semi-planar formats

 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices

 * 0 and 1, respectively. The CCS for all planes are stored outside of the

 * GEM object in a reserved memory area dedicated for the storage of the

 * CCS data for all compressible GEM objects.

 */

#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)



/*

 * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression

 * on discrete graphics

 *

 * The main surface is Tile 4 and at plane index 0. For semi-planar formats

 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices

 * 0 and 1, respectively. The CCS for all planes are stored outside of the

 * GEM object in a reserved memory area dedicated for the storage of the

 * CCS data for all compressible GEM objects. The GEM object must be stored in

 * contiguous memory with a size aligned to 64KB

 */

#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)



/*

 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks

 *