Unverified Commit 51624ddc authored Nov 03, 2024 by Alexandre Ghiti Committed by Palmer Dabbelt Nov 11, 2024

dt-bindings: riscv: Add Zabha ISA extension description



Add description for the Zabha ISA extension which was ratified in April
2024.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-5-alexghiti@rivosinc.com


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent 38acdee3

Documentation/devicetree/bindings/riscv/extensions.yaml

+6 −0

Original line number	Diff line number	Diff line
		@@ -178,6 +178,12 @@ properties:
		as ratified at commit 4a69197e5617 ("Update to ratified state") of
		riscv-svvptc.

		- const: zabha
		description: \|
		The Zabha extension for Byte and Halfword Atomic Memory Operations
		as ratified at commit 49f49c842ff9 ("Update to Rafified state") of
		riscv-zabha.

		- const: zacas
		description: \|
		The Zacas extension for Atomic Compare-and-Swap (CAS) instructions