Commit 51682bc4 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Use the per-GPU value for gmu_cgc_mode 



This register's magic value differs wildly between different GPUs, use
the hardcoded data instead of trying to make some logic out of it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611096/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent d50a8363

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −4
Original line number Diff line number Diff line
@@ -402,7 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;

	const struct adreno_reglist *reg;

	unsigned int i;

	u32 val, clock_cntl_on, cgc_mode;

	u32 val, clock_cntl_on;



	if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))

		return;
@@ -417,10 +417,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
		clock_cntl_on = 0x8aa8aa82;



	if (adreno_is_a7xx(adreno_gpu)) {

		cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;



		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,

			  state ? cgc_mode : 0);

			  state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);

		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,

			  state ? 0x10111 : 0);

		gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,