Merge tag 'net-next-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

What:		/sys/bus/auxiliary/devices/.../irqs/

Date:		April, 2024

Contact:	Shay Drory <shayd@nvidia.com>

Description:

		The /sys/devices/.../irqs directory contains a variable set of

		files, with each file is named as irq number similar to PCI PF

		or VF's irq number located in msi_irqs directory.

		These irq files are added and removed dynamically when an IRQ

		is requested and freed respectively for the PCI SF.

space part of the BPF application easier. Note that the BPF program themselves

must still be written in plain C.

libbpf logging

==============

By default, libbpf logs informational and warning messages to stderr. The

verbosity of these messages can be controlled by setting the environment

variable LIBBPF_LOG_LEVEL to either warn, info, or debug. A custom log

callback can be set using ``libbpf_set_print()``.

Additional Documentation

========================

R0 - R5 are scratch registers and BPF programs needs to spill/fill them if

necessary across calls.

The BPF program needs to store the return value into register R0 before doing an

``EXIT``.

BPF Instruction Set Architecture (ISA)

======================================

eBPF (which is no longer an acronym for anything), also commonly

eBPF, also commonly

referred to as BPF, is a technology with origins in the Linux kernel

that can run untrusted programs in a privileged context such as an

operating system kernel. This document specifies the BPF instruction

set architecture (ISA).

As a historical note, BPF originally stood for Berkeley Packet Filter,

but now that it can do so much more than packet filtering, the acronym

no longer makes sense. BPF is now considered a standalone term that

does not stand for anything.  The original BPF is sometimes referred to

as cBPF (classic BPF) to distinguish it from the now widely deployed

eBPF (extended BPF).

Documentation conventions

=========================

The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT",

"SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and

"OPTIONAL" in this document are to be interpreted as described in

BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_

`<https://www.rfc-editor.org/info/rfc8174>`_

when, and only when, they appear in all capitals, as shown here.

For brevity and consistency, this document refers to families

of types using a shorthand syntax and refers to several expository,

mnemonic functions when describing the semantics of instructions.

This document refers to integer types with the notation `SN` to specify

a type's signedness (`S`) and bit width (`N`), respectively.

.. table:: Meaning of signedness notation.

.. table:: Meaning of signedness notation

  ==== =========

  S    Meaning

  s    signed

  ==== =========

.. table:: Meaning of bit-width notation.

.. table:: Meaning of bit-width notation

  ===== =========

  N     Bit width

Functions

---------

* htobe16: Takes an unsigned 16-bit number in host-endian format and

  returns the equivalent number as an unsigned 16-bit number in big-endian

  format.

* htobe32: Takes an unsigned 32-bit number in host-endian format and

  returns the equivalent number as an unsigned 32-bit number in big-endian

  format.

* htobe64: Takes an unsigned 64-bit number in host-endian format and

  returns the equivalent number as an unsigned 64-bit number in big-endian

  format.

* htole16: Takes an unsigned 16-bit number in host-endian format and

  returns the equivalent number as an unsigned 16-bit number in little-endian

  format.

* htole32: Takes an unsigned 32-bit number in host-endian format and

  returns the equivalent number as an unsigned 32-bit number in little-endian

  format.

* htole64: Takes an unsigned 64-bit number in host-endian format and

  returns the equivalent number as an unsigned 64-bit number in little-endian

  format.

The following byteswap functions are direction-agnostic.  That is,

the same function is used for conversion in either direction discussed

below.

* be16: Takes an unsigned 16-bit number and converts it between

  host byte order and big-endian

  (`IEN137 <https://www.rfc-editor.org/ien/ien137.txt>`_) byte order.

* be32: Takes an unsigned 32-bit number and converts it between

  host byte order and big-endian byte order.

* be64: Takes an unsigned 64-bit number and converts it between

  host byte order and big-endian byte order.

* bswap16: Takes an unsigned 16-bit number in either big- or little-endian

  format and returns the equivalent number with the same bit width but

  opposite endianness.

* bswap64: Takes an unsigned 64-bit number in either big- or little-endian

  format and returns the equivalent number with the same bit width but

  opposite endianness.

* le16: Takes an unsigned 16-bit number and converts it between

  host byte order and little-endian byte order.

* le32: Takes an unsigned 32-bit number and converts it between

  host byte order and little-endian byte order.

* le64: Takes an unsigned 64-bit number and converts it between

  host byte order and little-endian byte order.

Definitions

-----------

An implementation does not need to support all instructions specified in this

document (e.g., deprecated instructions).  Instead, a number of conformance

groups are specified.  An implementation must support the base32 conformance

group and may support additional conformance groups, where supporting a

conformance group means it must support all instructions in that conformance

groups are specified.  An implementation MUST support the base32 conformance

group and MAY support additional conformance groups, where supporting a

conformance group means it MUST support all instructions in that conformance

group.

The use of named conformance groups enables interoperability between a runtime

  07     1       0        00 00  11 22 33 44  r1 += 0x11223344 // big

Note that most instructions do not use all of the fields.

Unused fields shall be cleared to zero.

Unused fields SHALL be cleared to zero.

Wide instruction encoding

--------------------------

The three least significant bits of the 'opcode' field store the instruction class:

.. table:: Instruction class

  =====  =====  ===============================  ===================================

  class  value  description                      reference

  =====  =====  ===============================  ===================================

**s (source)**

  the source operand location, which unless otherwise specified is one of:

  .. table:: Source operand location

    ======  =====  ==============================================

    source  value  description

    ======  =====  ==============================================

the source operand and 'dst' refers to the value of the destination

register.

.. table:: Arithmetic instructions

  =====  =====  =======  ==========================================================

  name   code   offset   description

  =====  =====  =======  ==========================================================

Note that there are varying definitions of the signed modulo operation

when the dividend or divisor are negative, where implementations often

vary by language such that Python, Ruby, etc.  differ from C, Go, Java,

etc. This specification requires that signed modulo use truncated division

etc. This specification requires that signed modulo MUST use truncated division

(where -13 % 3 == -1) as implemented in C, Go, etc.::

   a % n = a - n * trunc(a / n)

operands into 64-bit operands.  Unlike other arithmetic instructions,

``MOVSX`` is only defined for register source operands (``X``).

``{MOV, K, ALU64}`` means::

  dst = (s64)imm

``{MOV, X, ALU}`` means::

  dst = (u32)src

``{MOVSX, X, ALU}`` with 'offset' 8 means::

  dst = (u32)(s32)(s8)src

The ``NEG`` instruction is only defined when the source bit is clear

(``K``).

For ``ALU``, the 1-bit source operand field in the opcode is used to

select what byte order the operation converts from or to. For

``ALU64``, the 1-bit source operand field in the opcode is reserved

and must be set to 0.

and MUST be set to 0.

.. table:: Byte swap instructions

  =====  ========  =====  =================================================

  class  source    value  description

  =====  ========  =====  =================================================

ALU    TO_LE     0      convert between host byte order and little endian

ALU    TO_BE     1      convert between host byte order and big endian

  ALU    LE        0      convert between host byte order and little endian

  ALU    BE        1      convert between host byte order and big endian

  ALU64  Reserved  0      do byte swap unconditionally

  =====  ========  =====  =================================================

Examples:

``{END, TO_LE, ALU}`` with 'imm' = 16/32/64 means::

``{END, LE, ALU}`` with 'imm' = 16/32/64 means::

  dst = htole16(dst)

  dst = htole32(dst)

  dst = htole64(dst)

  dst = le16(dst)

  dst = le32(dst)

  dst = le64(dst)

``{END, TO_BE, ALU}`` with 'imm' = 16/32/64 means::

``{END, BE, ALU}`` with 'imm' = 16/32/64 means::

  dst = htobe16(dst)

  dst = htobe32(dst)

  dst = htobe64(dst)

  dst = be16(dst)

  dst = be32(dst)

  dst = be64(dst)

``{END, TO_LE, ALU64}`` with 'imm' = 16/32/64 means::

``{END, TO, ALU64}`` with 'imm' = 16/32/64 means::

  dst = bswap16(dst)

  dst = bswap32(dst)

group unless otherwise specified.

The 'code' field encodes the operation as below:

.. table:: Jump instructions

  ========  =====  =======  =================================  ===================================================

  code      value  src_reg  description                        notes

  ========  =====  =======  =================================  ===================================================

instruction if it's a basic instruction or results in undefined behavior

if the next instruction is a 128-bit wide instruction.

The BPF program needs to store the return value into register R0 before doing an

``EXIT``.

Example:

``{JSGE, X, JMP32}`` means::

where 's>=' indicates a signed '>=' comparison.

``{JLE, K, JMP}`` means::

  if dst <= (u64)(s64)imm goto +offset

``{JA, K, JMP32}`` means::

  gotol +imm

set of function calls exposed by the underlying platform.

Historically, each helper function was identified by a static ID

encoded in the 'imm' field.  The available helper functions may differ

for each program type, but static IDs are unique across all program types.

encoded in the 'imm' field.  Further documentation of helper functions

is outside the scope of this document and standardization is left for

future work, but use is widely deployed and more information can be

found in platform-specific documentation (e.g., Linux kernel documentation).

Platforms that support the BPF Type Format (BTF) support identifying

a helper function by a BTF ID encoded in the 'imm' field, where the BTF ID

identifies the helper name and type.

identifies the helper name and type.  Further documentation of BTF

is outside the scope of this document and standardization is left for

future work, but use is widely deployed and more information can be

found in platform-specific documentation (e.g., Linux kernel documentation).

Program-local functions

~~~~~~~~~~~~~~~~~~~~~~~

Program-local functions are functions exposed by the same BPF program as the

caller, and are referenced by offset from the call instruction, similar to

``JA``.  The offset is encoded in the 'imm' field of the call instruction.

An ``EXIT`` within the program-local function will return to the caller.

caller, and are referenced by offset from the instruction following the call

instruction, similar to ``JA``.  The offset is encoded in the 'imm' field of

the call instruction. An ``EXIT`` within the program-local function will

return to the caller.

Load and store instructions

===========================

**mode**

  The mode modifier is one of:

  .. table:: Mode modifier

    =============  =====  ====================================  =============

    mode modifier  value  description                           reference

    =============  =====  ====================================  =============

**sz (size)**

  The size modifier is one of:

  .. table:: Size modifier

    ====  =====  =====================

    size  value  description

    ====  =====  =====================

Simple atomic operation use a subset of the values defined to encode

arithmetic operations in the 'imm' field to encode the atomic operation:

.. table:: Simple atomic operations

  ========  =====  ===========

  imm       value  description

  ========  =====  ===========

In addition to the simple atomic operations, there also is a modifier and

two complex atomic operations:

.. table:: Complex atomic operations

  ===========  ================  ===========================

  imm          value             description

  ===========  ================  ===========================

with opcode subtypes in the 'src_reg' field, using new terms such as "map"

defined further below:

.. table:: 64-bit immediate instructions

  =======  =========================================  ===========  ==============

  src_reg  pseudocode                                 imm type     dst type

  =======  =========================================  ===========  ==============

class of ``LD``, a size modifier of ``W``, ``H``, or ``B``, and a

mode modifier of ``ABS`` or ``IND``.  The 'dst_reg' and 'offset' fields were

set to zero, and 'src_reg' was set to zero for ``ABS``.  However, these

instructions are deprecated and should no longer be used.  All legacy packet

instructions are deprecated and SHOULD no longer be used.  All legacy packet

access instructions belong to the "packet" conformance group.

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Airoha EN7581 Frame Engine Ethernet controller

maintainers:

  - Lorenzo Bianconi <lorenzo@kernel.org>

description:

  The frame engine ethernet controller can be found on Airoha SoCs.

  These SoCs have multi-GMAC ports.

properties:

  compatible:

    enum:

      - airoha,en7581-eth

  reg:

    items:

      - description: Frame engine base address

      - description: QDMA0 base address

      - description: QDMA1 base address

  reg-names:

    items:

      - const: fe

      - const: qdma0

      - const: qdma1

  interrupts:

    items:

      - description: QDMA lan irq0

      - description: QDMA lan irq1

      - description: QDMA lan irq2

      - description: QDMA lan irq3

      - description: QDMA wan irq0

      - description: QDMA wan irq1

      - description: QDMA wan irq2

      - description: QDMA wan irq3

      - description: FE error irq

      - description: PDMA irq

  resets:

    maxItems: 8

  reset-names:

    items:

      - const: fe

      - const: pdma

      - const: qdma

      - const: xsi-mac

      - const: hsi0-mac

      - const: hsi1-mac

      - const: hsi-mac

      - const: xfp-mac

  "#address-cells":

    const: 1

  "#size-cells":

    const: 0

patternProperties:

  "^ethernet@[1-4]$":

    type: object

    unevaluatedProperties: false

    $ref: ethernet-controller.yaml#

    description:

      Ethernet GMAC port associated to the MAC controller

    properties:

      compatible:

        const: airoha,eth-mac

      reg:

        minimum: 1

        maximum: 4

        description: GMAC port identifier

    required:

      - reg

      - compatible

required:

  - compatible

  - reg

  - interrupts

  - resets

  - reset-names

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/en7523-clk.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;

      eth: ethernet@1fb50000 {

        compatible = "airoha,en7581-eth";

        reg = <0 0x1fb50000 0 0x2600>,

              <0 0x1fb54000 0 0x2000>,

              <0 0x1fb56000 0 0x2000>;

        reg-names = "fe", "qdma0", "qdma1";

        resets = <&scuclk 44>,

                 <&scuclk 30>,

                 <&scuclk 31>,

                 <&scuclk 6>,

                 <&scuclk 15>,

                 <&scuclk 16>,

                 <&scuclk 17>,

                 <&scuclk 26>;

        reset-names = "fe", "pdma", "qdma", "xsi-mac",

                      "hsi0-mac", "hsi1-mac", "hsi-mac",

                      "xfp-mac";

        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

        #address-cells = <1>;

        #size-cells = <0>;

        mac: ethernet@1 {

          compatible = "airoha,eth-mac";

          reg = <1>;

        };

      };

    };