Commit 518e22b4 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu: remove re-route ih in psp v12 



APU doesn't have second IH ring, so re-routing action here is a no-op.
It will take a lot of time to wait timeout from PSP during the
initialization. So remove the function in psp v12.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b54695da

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

+0 −34
Original line number Diff line number Diff line
@@ -34,9 +34,6 @@ 
#include "sdma0/sdma0_4_0_offset.h"

#include "nbio/nbio_7_4_offset.h"



#include "oss/osssys_4_0_offset.h"

#include "oss/osssys_4_0_sh_mask.h"



MODULE_FIRMWARE("amdgpu/renoir_asd.bin");

MODULE_FIRMWARE("amdgpu/renoir_ta.bin");

MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
@@ -142,35 +139,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 
	return ret;

}



static void psp_v12_0_reroute_ih(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;

	uint32_t tmp;



	/* Change IH ring for VMC */

	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);



	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);



	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

		     0x80000000, 0x8000FFFF, false);



	/* Change IH ring for UMC */

	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);



	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);



	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

		     0x80000000, 0x8000FFFF, false);

}



static int psp_v12_0_ring_create(struct psp_context *psp,

				enum psp_ring_type ring_type)

{
@@ -179,8 +147,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp, 
	struct psp_ring *ring = &psp->km_ring;

	struct amdgpu_device *adev = psp->adev;



	psp_v12_0_reroute_ih(psp);



	if (amdgpu_sriov_vf(psp->adev)) {

		/* Write low address of the ring to C2PMSG_102 */

		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);