Unverified Commit 51bc04d5 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Krzysztof Wilczyński
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dt-bindings: PCI: qcom,pcie-sm8150: Move SM8150 to dedicated schema 

Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.

This creates equivalent schema file, except:
 - Missing required compatible which is actually redundant.
 - Expecting eight MSI interrupts, instead of only one, which was
   incomplete hardware description.

Link: https://lore.kernel.org/linux-pci/20240126-dt-bindings-pci-qcom-split-v3-4-f23cda4d74c0@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 4891b661

Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml

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+158 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8150 PCI Express Root Complex



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys

  DesignWare PCIe IP.



properties:

  compatible:

    const: qcom,pcie-sm8150



  reg:

    minItems: 5

    maxItems: 6



  reg-names:

    minItems: 5

    items:

      - const: parf # Qualcomm specific registers

      - const: dbi # DesignWare PCIe registers

      - const: elbi # External local bus interface registers

      - const: atu # ATU address space

      - const: config # PCIe configuration space

      - const: mhi # MHI registers



  clocks:

    minItems: 8

    maxItems: 8



  clock-names:

    items:

      - const: pipe # PIPE clock

      - const: aux # Auxiliary clock

      - const: cfg # Configuration clock

      - const: bus_master # Master AXI clock

      - const: bus_slave # Slave AXI clock

      - const: slave_q2a # Slave Q2A clock

      - const: tbu # PCIe TBU clock

      - const: ref # REFERENCE clock



  interrupts:

    minItems: 8

    maxItems: 8



  interrupt-names:

    items:

      - const: msi0

      - const: msi1

      - const: msi2

      - const: msi3

      - const: msi4

      - const: msi5

      - const: msi6

      - const: msi7



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pci



allOf:

  - $ref: qcom,pcie-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8150.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interconnect/qcom,sm8150.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        pcie@1c00000 {

            compatible = "qcom,pcie-sm8150";

            reg = <0 0x01c00000 0 0x3000>,

                  <0 0x60000000 0 0xf1d>,

                  <0 0x60000f20 0 0xa8>,

                  <0 0x60001000 0 0x1000>,

                  <0 0x60100000 0 0x100000>;

            reg-names = "parf", "dbi", "elbi", "atu", "config";

            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,

                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;



            bus-range = <0x00 0xff>;

            device_type = "pci";

            linux,pci-domain = <0>;

            num-lanes = <1>;



            #address-cells = <3>;

            #size-cells = <2>;



            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,

                     <&gcc GCC_PCIE_0_AUX_CLK>,

                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,

                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,

                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,

                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

                     <&rpmhcc RPMH_CXO_CLK>;

            clock-names = "pipe",

                          "aux",

                          "cfg",

                          "bus_master",

                          "bus_slave",

                          "slave_q2a",

                          "tbu",

                          "ref";



            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi0", "msi1", "msi2", "msi3",

                              "msi4", "msi5", "msi6", "msi7";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

                            <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

                            <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

                            <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



            iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,

                        <0x100 &apps_smmu 0x1d81 0x1>;



            phys = <&pcie0_phy>;

            phy-names = "pciephy";



            pinctrl-0 = <&pcie0_default_state>;

            pinctrl-names = "default";



            power-domains = <&gcc PCIE_0_GDSC>;



            resets = <&gcc GCC_PCIE_0_BCR>;

            reset-names = "pci";



            perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;

            wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;

        };

    };

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

+0 −29
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ properties: 
          - qcom,pcie-sc8280xp

          - qcom,pcie-sdm845

          - qcom,pcie-sdx55

          - qcom,pcie-sm8150

          - qcom,pcie-sm8350

      - items:

          - const: qcom,pcie-msm8998
@@ -541,33 +540,6 @@ allOf: 
          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,pcie-sm8150

    then:

      properties:

        clocks:

          minItems: 8

          maxItems: 8

        clock-names:

          items:

            - const: pipe # PIPE clock

            - const: aux # Auxiliary clock

            - const: cfg # Configuration clock

            - const: bus_master # Master AXI clock

            - const: bus_slave # Slave AXI clock

            - const: slave_q2a # Slave Q2A clock

            - const: tbu # PCIe TBU clock

            - const: ref # REFERENCE clock

        resets:

          maxItems: 1

        reset-names:

          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:
@@ -729,7 +701,6 @@ allOf: 
              - qcom,pcie-sc7280

              - qcom,pcie-sc8180x

              - qcom,pcie-sdm845

              - qcom,pcie-sm8150

              - qcom,pcie-sm8350

    then:

      oneOf: