Commit 51c4d5f1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'usb-6.11-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 

Pull USB fixes from Greg KH:
 "Here are a handful of small USB fixes for 6.11-rc7. Included in here
  are:

   - dwc3 driver fixes for two reported problems

   - two typec ucsi driver fixes

   - cdns2 controller reset fix

  All of these have been in linux-next this week with no reported
  problems"

* tag 'usb-6.11-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb:
  usb: typec: ucsi: Fix cable registration
  usb: typec: ucsi: Fix the partner PD revision
  usb: cdns2: Fix controller reset issue
  usb: dwc3: core: update LC timer as per USB Spec V3.2
  usb: dwc3: Avoid waking up gadget during startxfer
parents d1f2d51b 87eb3cb4

drivers/usb/dwc3/core.c

+15 −0
Original line number Diff line number Diff line
@@ -1386,6 +1386,21 @@ static int dwc3_core_init(struct dwc3 *dwc) 
		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

	}



	/*

	 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a

	 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the

	 * link compliance test (TD7.21) may fail. If the ECN is not

	 * enabled (GUCTL2[19] = 0), the controller will use the old timer

	 * value (5us), which is still acceptable for the link compliance

	 * test. Therefore, do not enable PM TIMER ECM in 3.20a by

	 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.

	 */

	if (DWC3_VER_IS(DWC3, 320A)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);

		reg &= ~DWC3_GUCTL2_LC_TIMER;

		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

	}



	/*

	 * When configured in HOST mode, after issuing U3/L2 exit controller

	 * fails to send proper CRC checksum in CRC5 feild. Because of this

drivers/usb/dwc3/core.h

+2 −0
Original line number Diff line number Diff line
@@ -421,6 +421,7 @@ 


/* Global User Control Register 2 */

#define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)

#define DWC3_GUCTL2_LC_TIMER			BIT(19)



/* Global User Control Register 3 */

#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
@@ -1269,6 +1270,7 @@ struct dwc3 { 
#define DWC3_REVISION_290A	0x5533290a

#define DWC3_REVISION_300A	0x5533300a

#define DWC3_REVISION_310A	0x5533310a

#define DWC3_REVISION_320A	0x5533320a

#define DWC3_REVISION_330A	0x5533330a



#define DWC31_REVISION_ANY	0x0

drivers/usb/dwc3/gadget.c

+17 −24
Original line number Diff line number Diff line
@@ -287,6 +287,23 @@ static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async); 
 *

 * Caller should handle locking. This function will issue @cmd with given

 * @params to @dep and wait for its completion.

 *

 * According to the programming guide, if the link state is in L1/L2/U3,

 * then sending the Start Transfer command may not complete. The

 * programming guide suggested to bring the link state back to ON/U0 by

 * performing remote wakeup prior to sending the command. However, don't

 * initiate remote wakeup when the user/function does not send wakeup

 * request via wakeup ops. Send the command when it's allowed.

 *

 * Notes:

 * For L1 link state, issuing a command requires the clearing of

 * GUSB2PHYCFG.SUSPENDUSB2, which turns on the signal required to complete

 * the given command (usually within 50us). This should happen within the

 * command timeout set by driver. No additional step is needed.

 *

 * For L2 or U3 link state, the gadget is in USB suspend. Care should be

 * taken when sending Start Transfer command to ensure that it's done after

 * USB resume.

 */

int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,

		struct dwc3_gadget_ep_cmd_params *params)
@@ -327,30 +344,6 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 
			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	}



	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {

		int link_state;



		/*

		 * Initiate remote wakeup if the link state is in U3 when

		 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the

		 * link state is in U1/U2, no remote wakeup is needed. The Start

		 * Transfer command will initiate the link recovery.

		 */

		link_state = dwc3_gadget_get_link_state(dwc);

		switch (link_state) {

		case DWC3_LINK_STATE_U2:

			if (dwc->gadget->speed >= USB_SPEED_SUPER)

				break;



			fallthrough;

		case DWC3_LINK_STATE_U3:

			ret = __dwc3_gadget_wakeup(dwc, false);

			dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",

					ret);

			break;

		}

	}



	/*

	 * For some commands such as Update Transfer command, DEPCMDPARn

	 * registers are reserved. Since the driver often sends Update Transfer

drivers/usb/gadget/udc/cdns2/cdns2-gadget.c

+3 −9
Original line number Diff line number Diff line
@@ -2251,7 +2251,6 @@ static int cdns2_gadget_start(struct cdns2_device *pdev) 
{

	u32 max_speed;

	void *buf;

	int val;

	int ret;



	pdev->usb_regs = pdev->regs;
@@ -2261,14 +2260,9 @@ static int cdns2_gadget_start(struct cdns2_device *pdev) 
	pdev->adma_regs = pdev->regs + CDNS2_ADMA_REGS_OFFSET;



	/* Reset controller. */

	set_reg_bit_8(&pdev->usb_regs->cpuctrl, CPUCTRL_SW_RST);



	ret = readl_poll_timeout_atomic(&pdev->usb_regs->cpuctrl, val,

					!(val & CPUCTRL_SW_RST), 1, 10000);

	if (ret) {

		dev_err(pdev->dev, "Error: reset controller timeout\n");

		return -EINVAL;

	}

	writeb(CPUCTRL_SW_RST | CPUCTRL_UPCLK | CPUCTRL_WUEN,

	       &pdev->usb_regs->cpuctrl);

	usleep_range(5, 10);



	usb_initialize_gadget(pdev->dev, &pdev->gadget, NULL);

drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

+9 −0
Original line number Diff line number Diff line
@@ -292,8 +292,17 @@ struct cdns2_usb_regs { 
#define SPEEDCTRL_HSDISABLE	BIT(7)



/* CPUCTRL- bitmasks. */

/* UP clock enable */

#define CPUCTRL_UPCLK		BIT(0)

/* Controller reset bit. */

#define CPUCTRL_SW_RST		BIT(1)

/**

 * If the wuen bit is ‘1’, the upclken is automatically set to ‘1’ after

 * detecting rising edge of wuintereq interrupt. If the wuen bit is ‘0’,

 * the wuintereq interrupt is ignored.

 */

#define CPUCTRL_WUEN		BIT(7)





/**

 * struct cdns2_adma_regs - ADMA controller registers.