Commit 51d976ec authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Dmitry Baryshkov
Browse files

drm/msm/dp: move/inline panel related functions 



Move panel-related functions to dp_panel.c, following up the cleanup
done by the rest of the submodules.

Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # sc7180-trogdor
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/654321/
Link: https://lore.kernel.org/r/20250518-fd-dp-audio-fixup-v6-6-2f0ec3ec000d@oss.qualcomm.com
parent 39b9a68b

drivers/gpu/drm/msm/dp/dp_catalog.c

+0 −195
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 
#define DP_INTERRUPT_STATUS_ACK_SHIFT	1

#define DP_INTERRUPT_STATUS_MASK_SHIFT	2



#define DP_INTF_CONFIG_DATABUS_WIDEN     BIT(4)



#define DP_INTERRUPT_STATUS1 \

	(DP_INTR_AUX_XFER_DONE| \

	DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
@@ -590,199 +588,6 @@ u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_catalog) 
	return msm_dp_read_link(msm_dp_catalog, REG_DP_MAINLINK_READY);

}



/* panel related catalog functions */

int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32 total,

				u32 sync_start, u32 width_blanking, u32 msm_dp_active)

{

	u32 reg;



	msm_dp_write_link(msm_dp_catalog, REG_DP_TOTAL_HOR_VER, total);

	msm_dp_write_link(msm_dp_catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);

	msm_dp_write_link(msm_dp_catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);

	msm_dp_write_link(msm_dp_catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active);



	reg = msm_dp_read_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG);



	if (msm_dp_catalog->wide_bus_en)

		reg |= DP_INTF_CONFIG_DATABUS_WIDEN;

	else

		reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN;





	DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", msm_dp_catalog->wide_bus_en, reg);



	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_CONFIG, reg);

	return 0;

}



static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp)

{

	u32 header[2];

	u32 val;

	int i;



	msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header);



	msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]);

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]);



	for (i = 0; i < sizeof(vsc_sdp->db); i += 4) {

		val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) |

		       (vsc_sdp->db[i + 3] << 24));

		msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val);

	}

}



static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_catalog)

{

	u32 hw_revision;



	hw_revision = msm_dp_catalog->hw_revision;



	if (hw_revision < DP_HW_VERSION_1_2 &&

	    hw_revision >= DP_HW_VERSION_1_0) {

		msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x01);

		msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG3, 0x00);

	}

}



void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp)

{

	struct msm_dp_catalog_private *catalog;

	u32 cfg, cfg2, misc;



	catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog);



	cfg = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG);

	cfg2 = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2);

	misc = msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0);



	cfg |= GEN0_SDP_EN;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg);



	cfg2 |= GENERIC0_SDPSIZE_VALID;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2);



	msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp);



	/* indicates presence of VSC (BIT(6) of MISC1) */

	misc |= DP_MISC1_VSC_SDP;



	drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=1\n");



	pr_debug("misc settings = 0x%x\n", misc);

	msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc);



	msm_dp_catalog_panel_update_sdp(msm_dp_catalog);

}



void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog)

{

	struct msm_dp_catalog_private *catalog;

	u32 cfg, cfg2, misc;



	catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog);



	cfg = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG);

	cfg2 = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2);

	misc = msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0);



	cfg &= ~GEN0_SDP_EN;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg);



	cfg2 &= ~GENERIC0_SDPSIZE_VALID;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2);



	/* switch back to MSA */

	misc &= ~DP_MISC1_VSC_SDP;



	drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=0\n");



	pr_debug("misc settings = 0x%x\n", misc);

	msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc);



	msm_dp_catalog_panel_update_sdp(msm_dp_catalog);

}



void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog,

				struct drm_display_mode *drm_mode)

{

	struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog,

				struct msm_dp_catalog_private, msm_dp_catalog);

	u32 hsync_period, vsync_period;

	u32 display_v_start, display_v_end;

	u32 hsync_start_x, hsync_end_x;

	u32 v_sync_width;

	u32 hsync_ctl;

	u32 display_hctl;



	/* TPG config parameters*/

	hsync_period = drm_mode->htotal;

	vsync_period = drm_mode->vtotal;



	display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) *

					hsync_period);

	display_v_end = ((vsync_period - (drm_mode->vsync_start -

					drm_mode->vdisplay))

					* hsync_period) - 1;



	display_v_start += drm_mode->htotal - drm_mode->hsync_start;

	display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay);



	hsync_start_x = drm_mode->htotal - drm_mode->hsync_start;

	hsync_end_x = hsync_period - (drm_mode->hsync_start -

					drm_mode->hdisplay) - 1;



	v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start;



	hsync_ctl = (hsync_period << 16) |

			(drm_mode->hsync_end - drm_mode->hsync_start);

	display_hctl = (hsync_end_x << 16) | hsync_start_x;





	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *

			hsync_period);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width *

			hsync_period);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);

	msm_dp_write_p0(msm_dp_catalog, MMSS_INTF_DISPLAY_V_START_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_INTF_POLARITY_CTL, 0);



	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL,

				DP_TPG_CHECKERED_RECT_PATTERN);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_VIDEO_CONFIG,

				DP_TPG_VIDEO_CONFIG_BPP_8BIT |

				DP_TPG_VIDEO_CONFIG_RGB);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE,

				DP_BIST_ENABLE_DPBIST_EN);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN,

				DP_TIMING_ENGINE_EN_EN);

	drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__);

}



void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog)

{

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_BIST_ENABLE, 0x0);

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);

}



void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_catalog)

{

	msm_dp_write_p0(msm_dp_catalog, MMSS_DP_DSC_DTO, 0x0);

}



static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_t *len)

{

	struct resource *res;

drivers/gpu/drm/msm/dp/dp_catalog.h

+0 −11
Original line number Diff line number Diff line
@@ -148,17 +148,6 @@ void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_catalog, 
				u32 pattern);

u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_catalog);



/* DP Panel APIs */

int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32 total,

				u32 sync_start, u32 width_blanking, u32 msm_dp_active);

void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp);

void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog);

void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog,

				struct drm_display_mode *drm_mode);

void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog);



void msm_dp_catalog_panel_clear_dsc_dto(struct msm_dp_catalog *msm_dp_catalog);



struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev);



/* DP Audio APIs */

drivers/gpu/drm/msm/dp/dp_ctrl.c

+3 −3
Original line number Diff line number Diff line
@@ -2050,7 +2050,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train 
		pixel_rate_orig,

		ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420);



	msm_dp_catalog_panel_clear_dsc_dto(ctrl->catalog);

	msm_dp_panel_clear_dsc_dto(ctrl->panel);



	msm_dp_ctrl_setup_tr_unit(ctrl);
@@ -2076,7 +2076,7 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) 
	ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);

	phy = ctrl->phy;



	msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog);

	msm_dp_panel_disable_vsc_sdp(ctrl->panel);



	/* set dongle to D3 (power off) mode */

	msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
@@ -2131,7 +2131,7 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) 
	ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);

	phy = ctrl->phy;



	msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog);

	msm_dp_panel_disable_vsc_sdp(ctrl->panel);



	msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);

drivers/gpu/drm/msm/dp/dp_panel.c

+198 −11
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include "dp_panel.h"

#include "dp_reg.h"

#include "dp_utils.h"



#include <drm/drm_connector.h>
@@ -11,6 +12,8 @@ 
#include <drm/drm_of.h>

#include <drm/drm_print.h>



#define DP_INTF_CONFIG_DATABUS_WIDEN     BIT(4)



#define DP_MAX_NUM_DP_LANES	4

#define DP_LINK_RATE_HBR2	540000 /* kbytes */
@@ -252,9 +255,87 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) 
	}

}



static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel,

				    struct drm_display_mode *drm_mode)

{

	struct msm_dp_panel_private *panel =

		container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	struct msm_dp_catalog *catalog = panel->catalog;

	u32 hsync_period, vsync_period;

	u32 display_v_start, display_v_end;

	u32 hsync_start_x, hsync_end_x;

	u32 v_sync_width;

	u32 hsync_ctl;

	u32 display_hctl;



	/* TPG config parameters*/

	hsync_period = drm_mode->htotal;

	vsync_period = drm_mode->vtotal;



	display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) *

					hsync_period);

	display_v_end = ((vsync_period - (drm_mode->vsync_start -

					drm_mode->vdisplay))

					* hsync_period) - 1;



	display_v_start += drm_mode->htotal - drm_mode->hsync_start;

	display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay);



	hsync_start_x = drm_mode->htotal - drm_mode->hsync_start;

	hsync_end_x = hsync_period - (drm_mode->hsync_start -

					drm_mode->hdisplay) - 1;



	v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start;



	hsync_ctl = (hsync_period << 16) |

			(drm_mode->hsync_end - drm_mode->hsync_start);

	display_hctl = (hsync_end_x << 16) | hsync_start_x;





	msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period *

			hsync_period);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width *

			hsync_period);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0);

	msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end);

	msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0);

	msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0);



	msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL,

				DP_TPG_CHECKERED_RECT_PATTERN);

	msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG,

				DP_TPG_VIDEO_CONFIG_BPP_8BIT |

				DP_TPG_VIDEO_CONFIG_RGB);

	msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE,

				DP_BIST_ENABLE_DPBIST_EN);

	msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN,

				DP_TIMING_ENGINE_EN_EN);

	drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__);

}



static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel)

{

	struct msm_dp_panel_private *panel =

		container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	struct msm_dp_catalog *catalog = panel->catalog;



	msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0);

	msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0);

	msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0);

}



void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable)

{

	struct msm_dp_catalog *catalog;

	struct msm_dp_panel_private *panel;



	if (!msm_dp_panel) {
@@ -263,7 +344,6 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 
	}



	panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	catalog = panel->catalog;



	if (!panel->panel_on) {

		drm_dbg_dp(panel->drm_dev,
@@ -272,18 +352,113 @@ void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 
	}



	if (!enable) {

		msm_dp_catalog_panel_tpg_disable(catalog);

		msm_dp_panel_tpg_disable(msm_dp_panel);

		return;

	}



	drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n");

	msm_dp_catalog_panel_tpg_enable(catalog, &panel->msm_dp_panel.msm_dp_mode.drm_mode);

	drm_dbg_dp(panel->drm_dev, "calling panel's tpg_enable\n");

	msm_dp_panel_tpg_enable(msm_dp_panel, &panel->msm_dp_panel.msm_dp_mode.drm_mode);

}



void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel)

{

	struct msm_dp_panel_private *panel =

		container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	struct msm_dp_catalog *catalog = panel->catalog;



	msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0);

}



static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp)

{

	struct msm_dp_catalog *msm_dp_catalog = panel->catalog;

	u32 header[2];

	u32 val;

	int i;



	msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header);



	msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_0, header[0]);

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_1, header[1]);



	for (i = 0; i < sizeof(vsc_sdp->db); i += 4) {

		val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) |

		       (vsc_sdp->db[i + 3] << 24));

		msm_dp_write_link(msm_dp_catalog, MMSS_DP_GENERIC0_2 + i, val);

	}

}



static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel)

{

	u32 hw_revision = panel->catalog->hw_revision;



	if (hw_revision >= DP_HW_VERSION_1_0 &&

	    hw_revision < DP_HW_VERSION_1_2) {

		msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP);

		msm_dp_write_link(panel->catalog, MMSS_DP_SDP_CFG3, 0x0);

	}

}



void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp)

{

	struct msm_dp_panel_private *panel =

		container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	struct msm_dp_catalog *msm_dp_catalog = panel->catalog;

	u32 cfg, cfg2, misc;



	cfg = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG);

	cfg2 = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2);

	misc = msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0);



	cfg |= GEN0_SDP_EN;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg);



	cfg2 |= GENERIC0_SDPSIZE_VALID;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2);



	msm_dp_panel_send_vsc_sdp(panel, vsc_sdp);



	/* indicates presence of VSC (BIT(6) of MISC1) */

	misc |= DP_MISC1_VSC_SDP;



	drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n");



	pr_debug("misc settings = 0x%x\n", misc);

	msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc);



	msm_dp_panel_update_sdp(panel);

}



void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)

{

	struct msm_dp_panel_private *panel =

		container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	struct msm_dp_catalog *msm_dp_catalog = panel->catalog;

	u32 cfg, cfg2, misc;



	cfg = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG);

	cfg2 = msm_dp_read_link(msm_dp_catalog, MMSS_DP_SDP_CFG2);

	misc = msm_dp_read_link(msm_dp_catalog, REG_DP_MISC1_MISC0);



	cfg &= ~GEN0_SDP_EN;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG, cfg);



	cfg2 &= ~GENERIC0_SDPSIZE_VALID;

	msm_dp_write_link(msm_dp_catalog, MMSS_DP_SDP_CFG2, cfg2);



	/* switch back to MSA */

	misc &= ~DP_MISC1_VSC_SDP;



	drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n");



	pr_debug("misc settings = 0x%x\n", misc);

	msm_dp_write_link(msm_dp_catalog, REG_DP_MISC1_MISC0, misc);



	msm_dp_panel_update_sdp(panel);

}



static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel)

{

	struct msm_dp_catalog *catalog;

	struct msm_dp_panel_private *panel;

	struct msm_dp_display_mode *msm_dp_mode;

	struct drm_dp_vsc_sdp vsc_sdp_data;

	struct dp_sdp vsc_sdp;
@@ -294,8 +469,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 
		return -EINVAL;

	}



	panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	catalog = panel->catalog;

	msm_dp_mode = &msm_dp_panel->msm_dp_mode;



	memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data));
@@ -322,7 +495,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 
		return len;

	}



	msm_dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp);

	msm_dp_panel_enable_vsc_sdp(msm_dp_panel, &vsc_sdp);



	return 0;

}
@@ -337,6 +510,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel) 
	u32 sync_start;

	u32 msm_dp_active;

	u32 total;

	u32 reg;



	panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);

	catalog = panel->catalog;
@@ -382,7 +556,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel) 


	msm_dp_active = data;



	msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blanking, msm_dp_active);

	msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total);

	msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);

	msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);

	msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active);



	reg = msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);

	if (catalog->wide_bus_en)

		reg |= DP_INTF_CONFIG_DATABUS_WIDEN;

	else

		reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN;



	drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", catalog->wide_bus_en, reg);



	msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);



	if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420)

		msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel);

drivers/gpu/drm/msm/dp/dp_panel.h

+5 −0
Original line number Diff line number Diff line
@@ -57,6 +57,11 @@ int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, 
void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel);

void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable);



void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel);



void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sdp *vsc_sdp);

void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel);



/**

 * is_link_rate_valid() - validates the link rate

 * @lane_rate: link rate requested by the sink