Commit 51db13aa authored by Linus Walleij's avatar Linus Walleij Committed by Russell King (Oracle)
Browse files

ARM: 9388/2: mm: Type-annotate all per-processor assembly routines 



Type tag the remaining per-processor assembly using the CFI
symbol macros, in addition to those that were previously tagged
for cache maintenance calls.

This will be used to finally provide proper C prototypes for
all these calls as well so that CFI can be made to work.

Tested-by: default avatarKees Cook <keescook@chromium.org>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarSami Tolvanen <samitolvanen@google.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
parent b4d20eff

arch/arm/mm/proc-arm1020.S

+15 −9
Original line number Diff line number Diff line
@@ -57,18 +57,20 @@ 
/*

 * cpu_arm1020_proc_init()

 */

ENTRY(cpu_arm1020_proc_init)

SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)

	ret	lr

SYM_FUNC_END(cpu_arm1020_proc_init)



/*

 * cpu_arm1020_proc_fin()

 */

ENTRY(cpu_arm1020_proc_fin)

SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ret	lr

SYM_FUNC_END(cpu_arm1020_proc_fin)



/*

 * cpu_arm1020_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1020_proc_fin) 
 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1020_reset)

SYM_TYPED_FUNC_START(cpu_arm1020_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1020_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	ret	r0

ENDPROC(cpu_arm1020_reset)

SYM_FUNC_END(cpu_arm1020_reset)

	.popsection



/*

 * cpu_arm1020_do_idle()

 */

	.align	5

ENTRY(cpu_arm1020_do_idle)

SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)

	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt

	ret	lr

SYM_FUNC_END(cpu_arm1020_do_idle)



/* ================================= CACHE ================================ */
@@ -360,7 +363,7 @@ SYM_TYPED_FUNC_START(arm1020_dma_unmap_area) 
SYM_FUNC_END(arm1020_dma_unmap_area)



	.align	5

ENTRY(cpu_arm1020_dcache_clean_area)

SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	ip, #0

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -370,6 +373,7 @@ ENTRY(cpu_arm1020_dcache_clean_area) 
	bhi	1b

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1020_dcache_clean_area)



/* =============================== PageTable ============================== */
@@ -381,7 +385,7 @@ ENTRY(cpu_arm1020_dcache_clean_area) 
 * pgd: new page tables

 */

	.align	5

ENTRY(cpu_arm1020_switch_mm)

SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r3, c7, c10, 4
@@ -409,6 +413,7 @@ ENTRY(cpu_arm1020_switch_mm) 
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif /* CONFIG_MMU */

	ret	lr

SYM_FUNC_END(cpu_arm1020_switch_mm)



/*

 * cpu_arm1020_set_pte(ptep, pte)
@@ -416,7 +421,7 @@ ENTRY(cpu_arm1020_switch_mm) 
 * Set a PTE and flush it out

 */

	.align	5

ENTRY(cpu_arm1020_set_pte_ext)

SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)

#ifdef CONFIG_MMU

	armv3_set_pte_ext

	mov	r0, r0
@@ -427,6 +432,7 @@ ENTRY(cpu_arm1020_set_pte_ext) 
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

#endif /* CONFIG_MMU */

	ret	lr

SYM_FUNC_END(cpu_arm1020_set_pte_ext)



	.type	__arm1020_setup, #function

__arm1020_setup:

arch/arm/mm/proc-arm1020e.S

+15 −9
Original line number Diff line number Diff line
@@ -57,18 +57,20 @@ 
/*

 * cpu_arm1020e_proc_init()

 */

ENTRY(cpu_arm1020e_proc_init)

SYM_TYPED_FUNC_START(cpu_arm1020e_proc_init)

	ret	lr

SYM_FUNC_END(cpu_arm1020e_proc_init)



/*

 * cpu_arm1020e_proc_fin()

 */

ENTRY(cpu_arm1020e_proc_fin)

SYM_TYPED_FUNC_START(cpu_arm1020e_proc_fin)

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ret	lr

SYM_FUNC_END(cpu_arm1020e_proc_fin)



/*

 * cpu_arm1020e_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1020e_proc_fin) 
 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1020e_reset)

SYM_TYPED_FUNC_START(cpu_arm1020e_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1020e_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	ret	r0

ENDPROC(cpu_arm1020e_reset)

SYM_FUNC_END(cpu_arm1020e_reset)

	.popsection



/*

 * cpu_arm1020e_do_idle()

 */

	.align	5

ENTRY(cpu_arm1020e_do_idle)

SYM_TYPED_FUNC_START(cpu_arm1020e_do_idle)

	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt

	ret	lr

SYM_FUNC_END(cpu_arm1020e_do_idle)



/* ================================= CACHE ================================ */
@@ -347,7 +350,7 @@ SYM_TYPED_FUNC_START(arm1020e_dma_unmap_area) 
SYM_FUNC_END(arm1020e_dma_unmap_area)



	.align	5

ENTRY(cpu_arm1020e_dcache_clean_area)

SYM_TYPED_FUNC_START(cpu_arm1020e_dcache_clean_area)

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	ip, #0

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -356,6 +359,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area) 
	bhi	1b

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1020e_dcache_clean_area)



/* =============================== PageTable ============================== */
@@ -367,7 +371,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area) 
 * pgd: new page tables

 */

	.align	5

ENTRY(cpu_arm1020e_switch_mm)

SYM_TYPED_FUNC_START(cpu_arm1020e_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r3, c7, c10, 4
@@ -394,6 +398,7 @@ ENTRY(cpu_arm1020e_switch_mm) 
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1020e_switch_mm)



/*

 * cpu_arm1020e_set_pte(ptep, pte)
@@ -401,7 +406,7 @@ ENTRY(cpu_arm1020e_switch_mm) 
 * Set a PTE and flush it out

 */

	.align	5

ENTRY(cpu_arm1020e_set_pte_ext)

SYM_TYPED_FUNC_START(cpu_arm1020e_set_pte_ext)

#ifdef CONFIG_MMU

	armv3_set_pte_ext

	mov	r0, r0
@@ -410,6 +415,7 @@ ENTRY(cpu_arm1020e_set_pte_ext) 
#endif

#endif /* CONFIG_MMU */

	ret	lr

SYM_FUNC_END(cpu_arm1020e_set_pte_ext)



	.type	__arm1020e_setup, #function

__arm1020e_setup:

arch/arm/mm/proc-arm1022.S

+15 −9
Original line number Diff line number Diff line
@@ -57,18 +57,20 @@ 
/*

 * cpu_arm1022_proc_init()

 */

ENTRY(cpu_arm1022_proc_init)

SYM_TYPED_FUNC_START(cpu_arm1022_proc_init)

	ret	lr

SYM_FUNC_END(cpu_arm1022_proc_init)



/*

 * cpu_arm1022_proc_fin()

 */

ENTRY(cpu_arm1022_proc_fin)

SYM_TYPED_FUNC_START(cpu_arm1022_proc_fin)

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ret	lr

SYM_FUNC_END(cpu_arm1022_proc_fin)



/*

 * cpu_arm1022_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1022_proc_fin) 
 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1022_reset)

SYM_TYPED_FUNC_START(cpu_arm1022_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1022_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	ret	r0

ENDPROC(cpu_arm1022_reset)

SYM_FUNC_END(cpu_arm1022_reset)

	.popsection



/*

 * cpu_arm1022_do_idle()

 */

	.align	5

ENTRY(cpu_arm1022_do_idle)

SYM_TYPED_FUNC_START(cpu_arm1022_do_idle)

	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt

	ret	lr

SYM_FUNC_END(cpu_arm1022_do_idle)



/* ================================= CACHE ================================ */
@@ -346,7 +349,7 @@ SYM_TYPED_FUNC_START(arm1022_dma_unmap_area) 
SYM_FUNC_END(arm1022_dma_unmap_area)



	.align	5

ENTRY(cpu_arm1022_dcache_clean_area)

SYM_TYPED_FUNC_START(cpu_arm1022_dcache_clean_area)

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	ip, #0

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -355,6 +358,7 @@ ENTRY(cpu_arm1022_dcache_clean_area) 
	bhi	1b

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1022_dcache_clean_area)



/* =============================== PageTable ============================== */
@@ -366,7 +370,7 @@ ENTRY(cpu_arm1022_dcache_clean_area) 
 * pgd: new page tables

 */

	.align	5

ENTRY(cpu_arm1022_switch_mm)

SYM_TYPED_FUNC_START(cpu_arm1022_switch_mm)

#ifdef CONFIG_MMU

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
@@ -386,6 +390,7 @@ ENTRY(cpu_arm1022_switch_mm) 
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1022_switch_mm)



/*

 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
@@ -393,7 +398,7 @@ ENTRY(cpu_arm1022_switch_mm) 
 * Set a PTE and flush it out

 */

	.align	5

ENTRY(cpu_arm1022_set_pte_ext)

SYM_TYPED_FUNC_START(cpu_arm1022_set_pte_ext)

#ifdef CONFIG_MMU

	armv3_set_pte_ext

	mov	r0, r0
@@ -402,6 +407,7 @@ ENTRY(cpu_arm1022_set_pte_ext) 
#endif

#endif /* CONFIG_MMU */

	ret	lr

SYM_FUNC_END(cpu_arm1022_set_pte_ext)



	.type	__arm1022_setup, #function

__arm1022_setup:

arch/arm/mm/proc-arm1026.S

+15 −9
Original line number Diff line number Diff line
@@ -57,18 +57,20 @@ 
/*

 * cpu_arm1026_proc_init()

 */

ENTRY(cpu_arm1026_proc_init)

SYM_TYPED_FUNC_START(cpu_arm1026_proc_init)

	ret	lr

SYM_FUNC_END(cpu_arm1026_proc_init)



/*

 * cpu_arm1026_proc_fin()

 */

ENTRY(cpu_arm1026_proc_fin)

SYM_TYPED_FUNC_START(cpu_arm1026_proc_fin)

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register

	bic	r0, r0, #0x1000 		@ ...i............

	bic	r0, r0, #0x000e 		@ ............wca.

	mcr	p15, 0, r0, c1, c0, 0		@ disable caches

	ret	lr

SYM_FUNC_END(cpu_arm1026_proc_fin)



/*

 * cpu_arm1026_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1026_proc_fin) 
 */

	.align	5

	.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm1026_reset)

SYM_TYPED_FUNC_START(cpu_arm1026_reset)

	mov	ip, #0

	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1026_reset) 
	bic	ip, ip, #0x1100 		@ ...i...s........

	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

	ret	r0

ENDPROC(cpu_arm1026_reset)

SYM_FUNC_END(cpu_arm1026_reset)

	.popsection



/*

 * cpu_arm1026_do_idle()

 */

	.align	5

ENTRY(cpu_arm1026_do_idle)

SYM_TYPED_FUNC_START(cpu_arm1026_do_idle)

	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt

	ret	lr

SYM_FUNC_END(cpu_arm1026_do_idle)



/* ================================= CACHE ================================ */
@@ -341,7 +344,7 @@ SYM_TYPED_FUNC_START(arm1026_dma_unmap_area) 
SYM_FUNC_END(arm1026_dma_unmap_area)



	.align	5

ENTRY(cpu_arm1026_dcache_clean_area)

SYM_TYPED_FUNC_START(cpu_arm1026_dcache_clean_area)

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mov	ip, #0

1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -350,6 +353,7 @@ ENTRY(cpu_arm1026_dcache_clean_area) 
	bhi	1b

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1026_dcache_clean_area)



/* =============================== PageTable ============================== */
@@ -361,7 +365,7 @@ ENTRY(cpu_arm1026_dcache_clean_area) 
 * pgd: new page tables

 */

	.align	5

ENTRY(cpu_arm1026_switch_mm)

SYM_TYPED_FUNC_START(cpu_arm1026_switch_mm)

#ifdef CONFIG_MMU

	mov	r1, #0

#ifndef CONFIG_CPU_DCACHE_DISABLE
@@ -376,6 +380,7 @@ ENTRY(cpu_arm1026_switch_mm) 
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs

#endif

	ret	lr

SYM_FUNC_END(cpu_arm1026_switch_mm)



/*

 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
@@ -383,7 +388,7 @@ ENTRY(cpu_arm1026_switch_mm) 
 * Set a PTE and flush it out

 */

	.align	5

ENTRY(cpu_arm1026_set_pte_ext)

SYM_TYPED_FUNC_START(cpu_arm1026_set_pte_ext)

#ifdef CONFIG_MMU

	armv3_set_pte_ext

	mov	r0, r0
@@ -392,6 +397,7 @@ ENTRY(cpu_arm1026_set_pte_ext) 
#endif

#endif /* CONFIG_MMU */

	ret	lr

SYM_FUNC_END(cpu_arm1026_set_pte_ext)



	.type	__arm1026_setup, #function

__arm1026_setup:

arch/arm/mm/proc-arm720.S

+17 −8
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
 */

#include <linux/linkage.h>

#include <linux/init.h>

#include <linux/cfi_types.h>

#include <linux/pgtable.h>

#include <asm/assembler.h>

#include <asm/asm-offsets.h>
@@ -35,24 +36,30 @@ 
 *

 * Notes   : This processor does not require these

 */

ENTRY(cpu_arm720_dcache_clean_area)

ENTRY(cpu_arm720_proc_init)

SYM_TYPED_FUNC_START(cpu_arm720_dcache_clean_area)

		ret	lr

SYM_FUNC_END(cpu_arm720_dcache_clean_area)



ENTRY(cpu_arm720_proc_fin)

SYM_TYPED_FUNC_START(cpu_arm720_proc_init)

		ret	lr

SYM_FUNC_END(cpu_arm720_proc_init)



SYM_TYPED_FUNC_START(cpu_arm720_proc_fin)

		mrc	p15, 0, r0, c1, c0, 0

		bic	r0, r0, #0x1000			@ ...i............

		bic	r0, r0, #0x000e			@ ............wca.

		mcr	p15, 0, r0, c1, c0, 0		@ disable caches

		ret	lr

SYM_FUNC_END(cpu_arm720_proc_fin)



/*

 * Function: arm720_proc_do_idle(void)

 * Params  : r0 = unused

 * Purpose : put the processor in proper idle mode

 */

ENTRY(cpu_arm720_do_idle)

SYM_TYPED_FUNC_START(cpu_arm720_do_idle)

		ret	lr

SYM_FUNC_END(cpu_arm720_do_idle)



/*

 * Function: arm720_switch_mm(unsigned long pgd_phys)
@@ -60,7 +67,7 @@ ENTRY(cpu_arm720_do_idle) 
 * Purpose : Perform a task switch, saving the old process' state and restoring

 *	     the new.

 */

ENTRY(cpu_arm720_switch_mm)

SYM_TYPED_FUNC_START(cpu_arm720_switch_mm)

#ifdef CONFIG_MMU

		mov	r1, #0

		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
@@ -68,6 +75,7 @@ ENTRY(cpu_arm720_switch_mm) 
		mcr	p15, 0, r1, c8, c7, 0		@ flush TLB (v4)

#endif

		ret	lr

SYM_FUNC_END(cpu_arm720_switch_mm)



/*

 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
@@ -76,11 +84,12 @@ ENTRY(cpu_arm720_switch_mm) 
 * Purpose : Set a PTE and flush it out of any WB cache

 */

	.align	5

ENTRY(cpu_arm720_set_pte_ext)

SYM_TYPED_FUNC_START(cpu_arm720_set_pte_ext)

#ifdef CONFIG_MMU

	armv3_set_pte_ext wc_disable=0

#endif

	ret	lr

SYM_FUNC_END(cpu_arm720_set_pte_ext)



/*

 * Function: arm720_reset
@@ -88,7 +97,7 @@ ENTRY(cpu_arm720_set_pte_ext) 
 * Notes   : This sets up everything for a reset

 */

		.pushsection	.idmap.text, "ax"

ENTRY(cpu_arm720_reset)

SYM_TYPED_FUNC_START(cpu_arm720_reset)

		mov	ip, #0

		mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache

#ifdef CONFIG_MMU
@@ -99,7 +108,7 @@ ENTRY(cpu_arm720_reset) 
		bic	ip, ip, #0x2100			@ ..v....s........

		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register

		ret	r0

ENDPROC(cpu_arm720_reset)

SYM_FUNC_END(cpu_arm720_reset)

		.popsection



	.type	__arm710_setup, #function