Commit 51dcc15b authored by Adrián Larumbe's avatar Adrián Larumbe Committed by Boris Brezillon
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drm/panfrost: Add cycle count GPU register definitions 



These GPU registers will be used when programming the cycle counter, which
we need for providing accurate fdinfo drm-cycles values to user space.

Signed-off-by: default avatarAdrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: default avatarSteven Price <steven.price@arm.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230929181616.2769345-2-adrian.larumbe@collabora.com
parent 653e2486

drivers/gpu/drm/panfrost/panfrost_regs.h

+5 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define   GPU_CMD_SOFT_RESET		0x01

#define   GPU_CMD_PERFCNT_CLEAR		0x03

#define   GPU_CMD_PERFCNT_SAMPLE	0x04

#define   GPU_CMD_CYCLE_COUNT_START	0x05

#define   GPU_CMD_CYCLE_COUNT_STOP	0x06

#define   GPU_CMD_CLEAN_CACHES		0x07

#define   GPU_CMD_CLEAN_INV_CACHES	0x08

#define GPU_STATUS			0x34
@@ -73,6 +75,9 @@ 
#define GPU_PRFCNT_TILER_EN		0x74

#define GPU_PRFCNT_MMU_L2_EN		0x7c



#define GPU_CYCLE_COUNT_LO		0x90

#define GPU_CYCLE_COUNT_HI		0x94



#define GPU_THREAD_MAX_THREADS		0x0A0	/* (RO) Maximum number of threads per core */

#define GPU_THREAD_MAX_WORKGROUP_SIZE	0x0A4	/* (RO) Maximum workgroup size */

#define GPU_THREAD_MAX_BARRIER_SIZE	0x0A8	/* (RO) Maximum threads waiting at a barrier */