Unverified Commit 51e41dc2 authored by Nandhini Srikandan's avatar Nandhini Srikandan Committed by Mark Brown
Browse files

spi: dw: Add support for master mode selection for DWC SSI controller 



Add support to select the controller mode as master mode by setting Bit 31
of CTRLR0 register. This feature is supported for controller versions above
v1.02.

Signed-off-by: default avatarNandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0d085723

drivers/spi/spi-dw-core.c

+3 −2
Original line number Diff line number Diff line
@@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) 
		if (spi->mode & SPI_LOOP)

			cr0 |= DW_HSSI_CTRLR0_SRL;



		if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)

			cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;

		/* CTRLR0[31] MST */

		if (dw_spi_ver_is_ge(dws, HSSI, 102A))

			cr0 |= DW_HSSI_CTRLR0_MST;

	}



	return cr0;

drivers/spi/spi-dw.h

+1 −7
Original line number Diff line number Diff line
@@ -94,13 +94,7 @@ 
#define DW_HSSI_CTRLR0_SCPOL			BIT(9)

#define DW_HSSI_CTRLR0_TMOD_MASK		GENMASK(11, 10)

#define DW_HSSI_CTRLR0_SRL			BIT(13)



/*

 * For Keem Bay, CTRLR0[31] is used to select controller mode.

 * 0: SSI is slave

 * 1: SSI is master

 */

#define DW_HSSI_CTRLR0_KEEMBAY_MST		BIT(31)

#define DW_HSSI_CTRLR0_MST			BIT(31)



/* Bit fields in CTRLR1 */

#define DW_SPI_NDF_MASK				GENMASK(15, 0)