Commit 51e60796 authored by Oliver Upton's avatar Oliver Upton
Browse files

Merge branch kvm-arm64/nv-trap-fixes into kvmarm/next 



* kvm-arm64/nv-trap-fixes:
  : NV trap forwarding fixes, courtesy Miguel Luis and Marc Zyngier
  :
  :  - Explicitly define the effects of HCR_EL2.NV on EL2 sysregs in the
  :    NV trap encoding
  :
  :  - Make EL2 registers that access AArch32 guest state UNDEF or RAZ/WI
  :    where appropriate for NV guests
  KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI
  KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs
  KVM: arm64: Refine _EL2 system register list that require trap reinjection
  arm64: Add missing _EL2 encodings
  arm64: Add missing _EL12 encodings

Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parents 25a35c1a 3f7915cc

arch/arm64/include/asm/sysreg.h

+45 −0
Original line number Diff line number Diff line
@@ -270,6 +270,8 @@ 
/* ETM */

#define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)



#define SYS_BRBCR_EL2			sys_reg(2, 4, 9, 0, 0)



#define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)

#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)

#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
@@ -484,6 +486,7 @@ 


#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)

#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)

#define SYS_SCTLR2_EL2			sys_reg(3, 4, 1, 0, 3)

#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)

#define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)

#define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
@@ -497,10 +500,15 @@ 
#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)



#define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)

#define SYS_VNCR_EL2			sys_reg(3, 4, 2, 2, 0)

#define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)

#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)

#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)

#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)

#define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)

#define SYS_SPSR_abt			sys_reg(3, 4, 4, 3, 1)

#define SYS_SPSR_und			sys_reg(3, 4, 4, 3, 2)

#define SYS_SPSR_fiq			sys_reg(3, 4, 4, 3, 3)

#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)

#define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)

#define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
@@ -514,6 +522,18 @@ 


#define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)

#define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)

#define SYS_MPAMHCR_EL2			sys_reg(3, 4, 10, 4, 0)

#define SYS_MPAMVPMV_EL2		sys_reg(3, 4, 10, 4, 1)

#define SYS_MPAM2_EL2			sys_reg(3, 4, 10, 5, 0)

#define __SYS__MPAMVPMx_EL2(x)		sys_reg(3, 4, 10, 6, x)

#define SYS_MPAMVPM0_EL2		__SYS__MPAMVPMx_EL2(0)

#define SYS_MPAMVPM1_EL2		__SYS__MPAMVPMx_EL2(1)

#define SYS_MPAMVPM2_EL2		__SYS__MPAMVPMx_EL2(2)

#define SYS_MPAMVPM3_EL2		__SYS__MPAMVPMx_EL2(3)

#define SYS_MPAMVPM4_EL2		__SYS__MPAMVPMx_EL2(4)

#define SYS_MPAMVPM5_EL2		__SYS__MPAMVPMx_EL2(5)

#define SYS_MPAMVPM6_EL2		__SYS__MPAMVPMx_EL2(6)

#define SYS_MPAMVPM7_EL2		__SYS__MPAMVPMx_EL2(7)



#define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)

#define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
@@ -562,24 +582,49 @@ 


#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)

#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)

#define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)



#define __AMEV_op2(m)			(m & 0x7)

#define __AMEV_CRm(n, m)		(n | ((m & 0x8) >> 3))

#define __SYS__AMEVCNTVOFF0n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))

#define SYS_AMEVCNTVOFF0n_EL2(m)	__SYS__AMEVCNTVOFF0n_EL2(m)

#define __SYS__AMEVCNTVOFF1n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))

#define SYS_AMEVCNTVOFF1n_EL2(m)	__SYS__AMEVCNTVOFF1n_EL2(m)



#define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)

#define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)

#define SYS_CNTHP_TVAL_EL2		sys_reg(3, 4, 14, 2, 0)

#define SYS_CNTHP_CTL_EL2		sys_reg(3, 4, 14, 2, 1)

#define SYS_CNTHP_CVAL_EL2		sys_reg(3, 4, 14, 2, 2)

#define SYS_CNTHV_TVAL_EL2		sys_reg(3, 4, 14, 3, 0)

#define SYS_CNTHV_CTL_EL2		sys_reg(3, 4, 14, 3, 1)

#define SYS_CNTHV_CVAL_EL2		sys_reg(3, 4, 14, 3, 2)



/* VHE encodings for architectural EL0/1 system registers */

#define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)

#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)

#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)

#define SYS_SCTLR2_EL12			sys_reg(3, 5, 1, 0, 3)

#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)

#define SYS_TRFCR_EL12			sys_reg(3, 5, 1, 2, 1)

#define SYS_SMCR_EL12			sys_reg(3, 5, 1, 2, 6)

#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)

#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)

#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)

#define SYS_TCR2_EL12			sys_reg(3, 5, 2, 0, 3)

#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)

#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)

#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)

#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)

#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)

#define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)

#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)

#define SYS_PMSCR_EL12			sys_reg(3, 5, 9, 9, 0)

#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)

#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)

#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)

#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)

#define SYS_SCXTNUM_EL12		sys_reg(3, 5, 13, 0, 7)

#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)

#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)

#define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)

arch/arm64/kvm/emulate-nested.c

+71 −6
Original line number Diff line number Diff line
@@ -648,15 +648,80 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 
	SR_TRAP(SYS_APGAKEYLO_EL1,	CGT_HCR_APK),

	SR_TRAP(SYS_APGAKEYHI_EL1,	CGT_HCR_APK),

	/* All _EL2 registers */

	SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),

		      sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),

	SR_TRAP(SYS_BRBCR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_VPIDR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_VMPIDR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_SCTLR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_ACTLR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_SCTLR2_EL2,		CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_HCR_EL2,

		      SYS_HCRX_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_SMPRIMAP_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_SMCR_EL2,		CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_TTBR0_EL2,

		      SYS_TCR2_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_VTTBR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_VTCR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_VNCR_EL2,		CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_HDFGRTR_EL2,

		      SYS_HAFGRTR_EL2,	CGT_HCR_NV),

	/* Skip the SP_EL1 encoding... */

	SR_TRAP(SYS_SPSR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_ELR_EL2,		CGT_HCR_NV),

	SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),

		      sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),

	SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),

		      sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),

	/* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */

	SR_TRAP(SYS_AFSR0_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_AFSR1_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_ESR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_VSESR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_TFSR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_FAR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_HPFAR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_PMSCR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_MAIR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_AMAIR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_MPAMHCR_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_MPAMVPMV_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_MPAM2_EL2,		CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_MPAMVPM0_EL2,

		      SYS_MPAMVPM7_EL2,	CGT_HCR_NV),

	/*

	 * Note that the spec. describes a group of MEC registers

	 * whose access should not trap, therefore skip the following:

	 * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,

	 * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,

	 * VMECID_P_EL2.

	 */

	SR_RANGE_TRAP(SYS_VBAR_EL2,

		      SYS_RMR_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_VDISR_EL2,		CGT_HCR_NV),

	/* ICH_AP0R<m>_EL2 */

	SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,

		      SYS_ICH_AP0R3_EL2, CGT_HCR_NV),

	/* ICH_AP1R<m>_EL2 */

	SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,

		      SYS_ICH_AP1R3_EL2, CGT_HCR_NV),

	SR_TRAP(SYS_ICC_SRE_EL2,	CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_ICH_HCR_EL2,

		      SYS_ICH_EISR_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_ICH_ELRSR_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_ICH_VMCR_EL2,	CGT_HCR_NV),

	/* ICH_LR<m>_EL2 */

	SR_RANGE_TRAP(SYS_ICH_LR0_EL2,

		      SYS_ICH_LR15_EL2, CGT_HCR_NV),

	SR_TRAP(SYS_CONTEXTIDR_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_TPIDR_EL2,		CGT_HCR_NV),

	SR_TRAP(SYS_SCXTNUM_EL2,	CGT_HCR_NV),

	/* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2  */

	SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0),

		      SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV),

	/* CNT*_EL2 */

	SR_TRAP(SYS_CNTVOFF_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_CNTPOFF_EL2,	CGT_HCR_NV),

	SR_TRAP(SYS_CNTHCTL_EL2,	CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2,

		      SYS_CNTHP_CVAL_EL2, CGT_HCR_NV),

	SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2,

		      SYS_CNTHV_CVAL_EL2, CGT_HCR_NV),

	/* All _EL02, _EL12 registers */

	SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),

		      sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),

arch/arm64/kvm/sys_regs.c

+17 −7
Original line number Diff line number Diff line
@@ -1795,7 +1795,7 @@ static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, 
 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of

 * handling traps. Given that, they are always hidden from userspace.

 */

static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,

static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu,

					   const struct sys_reg_desc *rd)

{

	return REG_HIDDEN_USER;
@@ -1807,7 +1807,7 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, 
	.reset = rst,				\

	.reg = name##_EL1,			\

	.val = v,				\

	.visibility = elx2_visibility,		\

	.visibility = hidden_user_visibility,	\

}



/*
@@ -1965,7 +1965,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	// DBGDTR[TR]X_EL0 share the same encoding

	{ SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },



	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },

	{ SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 },



	{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
@@ -2384,18 +2384,28 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),

	EL2_REG(VTCR_EL2, access_rw, reset_val, 0),



	{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },

	{ SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },

	EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),

	EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),

	EL2_REG(SPSR_EL2, access_rw, reset_val, 0),

	EL2_REG(ELR_EL2, access_rw, reset_val, 0),

	{ SYS_DESC(SYS_SP_EL1), access_sp_el1},



	{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },

	/* AArch32 SPSR_* are RES0 if trapped from a NV guest */

	{ SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi,

	  .visibility = hidden_user_visibility },

	{ SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi,

	  .visibility = hidden_user_visibility },

	{ SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi,

	  .visibility = hidden_user_visibility },

	{ SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi,

	  .visibility = hidden_user_visibility },



	{ SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 },

	EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),

	EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),

	EL2_REG(ESR_EL2, access_rw, reset_val, 0),

	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },

	{ SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 },



	EL2_REG(FAR_EL2, access_rw, reset_val, 0),

	EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),