Commit 52239ebe authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzv2h: Support static dividers without RMW 



Add support for static dividers that do not require read-modify-write
(RMW) operations.  This enables the use of the generic clk_divider_ops
instead of the custom RMW-based implementation.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6e1c7950

drivers/clk/renesas/rzv2h-cpg.c

+4 −1
Original line number Diff line number Diff line
@@ -374,6 +374,9 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core, 
		return ERR_PTR(-ENOMEM);



	init.name = core->name;

	if (cfg_ddiv.no_rmw)

		init.ops = &clk_divider_ops;

	else

		init.ops = &rzv2h_ddiv_clk_divider_ops;

	init.parent_names = &parent_name;

	init.num_parents = 1;

drivers/clk/renesas/rzv2h-cpg.h

+12 −0
Original line number Diff line number Diff line
@@ -37,12 +37,15 @@ struct pll { 
 * @shift: position of the divider bit

 * @width: width of the divider

 * @monbit: monitor bit in CPG_CLKSTATUS0 register

 * @no_rmw: flag to indicate if the register is read-modify-write

 *        (1: no RMW, 0: RMW)

 */

struct ddiv {

	unsigned int offset:11;

	unsigned int shift:4;

	unsigned int width:4;

	unsigned int monbit:5;

	unsigned int no_rmw:1;

};



/*
@@ -61,6 +64,15 @@ struct ddiv { 
		.monbit = _monbit \

	})



#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \

	((struct ddiv){ \

		.offset = (_offset), \

		.shift = (_shift), \

		.width = (_width), \

		.monbit = (_monbit), \

		.no_rmw = 1 \

	})



/**

 * struct smuxed - Structure for static muxed clocks

 *