Commit 52345d35 authored by Amadeusz Sławiński's avatar Amadeusz Sławiński Committed by Takashi Iwai
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ALSA: hda: Fix all stream interrupts definition



It is defined in header to 0xFF, which only allows to set values for 8
streams. In specification it is defined as bits from 0 to 29. In
practice there is no HW with 29 streams, but as the only place where the
value is used is chip initialization, it is best to make sure that all
bits are reset properly.

Reviewed-by: default avatarCezary Rojewski <cezary.rojewski@intel.com>
Signed-off-by: default avatarAmadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Link: https://patch.msgid.link/20241014094958.708563-1-amadeuszx.slawinski@linux.intel.com


Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 0ddf2784
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+1 −1
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
#define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define AZX_INT_ALL_STREAM	0x3fffffff	   /* all stream interrupts */
#define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */