Commit 5245dc5f authored by Markus Niebel's avatar Markus Niebel Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off 



Fix SD card removal caused by automatic LDO5 power off after boot:

LDO5: disabling
mmc1: card 59b4 removed
EXT4-fs (mmcblk1p2): shut down requested (2)
Aborting journal on device mmcblk1p2-8.
JBD2: I/O error when updating journal superblock for mmcblk1p2-8.

To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.

Fixes: 418d1d84 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP")
Signed-off-by: default avatarMarkus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 8f5ae30d

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts

+7 −6
Original line number Diff line number Diff line
@@ -467,6 +467,10 @@ &pwm4 { 
	status = "okay";

};



&reg_usdhc2_vqmmc {

	status = "okay";

};



&sai5 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai5>;
@@ -876,8 +880,7 @@ pinctrl_usdhc2: usdhc2grp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -886,8 +889,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -896,8 +898,7 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>;

	};



	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

+7 −6
Original line number Diff line number Diff line
@@ -604,6 +604,10 @@ &pwm3 { 
	status = "okay";

};



&reg_usdhc2_vqmmc {

	status = "okay";

};



&sai3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_sai3>;
@@ -983,8 +987,7 @@ pinctrl_usdhc2: usdhc2grp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d2>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d2>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -993,8 +996,7 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -1003,8 +1005,7 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 
			   <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4>,

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>,

			   <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0>;

			   <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4>;

	};



	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -24,6 +24,20 @@ reg_vcc3v3: regulator-vcc3v3 { 
		regulator-max-microvolt = <3300000>;

		regulator-always-on;

	};



	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {

		compatible = "regulator-gpio";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;

		regulator-name = "V_SD2";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;

		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

		states = <1800000 0x1>,

			 <3300000 0x0>;

		vin-supply = <&ldo5_reg>;

		status = "disabled";

	};

};



&A53_0 {
@@ -184,6 +198,10 @@ m24c64: eeprom@57 { 
	};

};



&usdhc2 {

	vqmmc-supply = <&reg_usdhc2_vqmmc>;

};



&usdhc3 {

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc3>;
@@ -233,6 +251,10 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 
		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;

	};



	pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {

		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04		0xc0>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,

			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,