Commit 52b464f8 authored by Marek Vasut's avatar Marek Vasut Committed by Tomi Valkeinen
Browse files

drm/rcar-du: dsi: Clean up VCLKSET register macros 



Introduce VCLKSET_BPP_MASK macro and use FIELD_PREP() to generate
appropriate bitfield from mask and value without bitshift. Remove
VCLKSET_COLOR_RGB which is never used, replace it with code comment.

Do not convert bits and bitfields to BIT() and GENMASK() yet, to be
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.

Reviewed-by: default avatarTomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-6-marek.vasut+renesas@mailbox.org


Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
parent 1d89f8b4

drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c

+3 −1
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 * Copyright (C) 2020 Renesas Electronics Corporation

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/io.h>
@@ -624,6 +625,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, 
	vclkset = VCLKSET_CKEN;

	rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);



	/* Output is always RGB, never YCbCr */

	if (dsi_format == 24)

		vclkset |= VCLKSET_BPP_24;

	else if (dsi_format == 18)
@@ -635,7 +637,7 @@ static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, 
		return -EINVAL;

	}



	vclkset |= VCLKSET_COLOR_RGB | VCLKSET_LANE(dsi->lanes - 1);

	vclkset |= VCLKSET_LANE(dsi->lanes - 1);



	switch (dsi->info->model) {

	case RCAR_DSI_V3U:

drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h

+6 −6
Original line number Diff line number Diff line
@@ -246,14 +246,14 @@ 


#define VCLKSET				0x100c

#define VCLKSET_CKEN			(1 << 16)

#define VCLKSET_COLOR_RGB		(0 << 8)

#define VCLKSET_COLOR_YCC		(1 << 8)

#define VCLKSET_COLOR_YCC		(1 << 8) /* 0:RGB 1:YCbCr */

#define VCLKSET_DIV_V3U(x)		(((x) & 0x3) << 4)

#define VCLKSET_DIV_V4H(x)		(((x) & 0x7) << 4)

#define VCLKSET_BPP_16			(0 << 2)

#define VCLKSET_BPP_18			(1 << 2)

#define VCLKSET_BPP_18L			(2 << 2)

#define VCLKSET_BPP_24			(3 << 2)

#define VCLKSET_BPP_MASK		(3 << 2)

#define VCLKSET_BPP_16			FIELD_PREP(VCLKSET_BPP_MASK, 0)

#define VCLKSET_BPP_18			FIELD_PREP(VCLKSET_BPP_MASK, 1)

#define VCLKSET_BPP_18L			FIELD_PREP(VCLKSET_BPP_MASK, 2)

#define VCLKSET_BPP_24			FIELD_PREP(VCLKSET_BPP_MASK, 3)

#define VCLKSET_LANE(x)			(((x) & 0x3) << 0)



#define VCLKEN				0x1010