Commit 52c4abee authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/psr: Fix PSR sink enable sequence 



According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240911151836.16800-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
parent 2478e223

drivers/gpu/drm/i915/display/intel_psr.c

+3 −1
Original line number Diff line number Diff line
@@ -764,7 +764,7 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, 
			     const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(intel_dp);

	u8 val = DP_PSR_ENABLE;

	u8 val = 0;



	if (crtc_state->has_sel_update) {

		val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
@@ -784,7 +784,9 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, 


	if (intel_dp->psr.entry_setup_frames > 0)

		val |= DP_PSR_FRAME_CAPTURE;

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);



	val |= DP_PSR_ENABLE;

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

}