Commit 530258f8 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Tony Luck
Browse files

EDAC, pnd2: Apply bit macros and helpers where it makes sense 



Apply bit macros (BIT()/BIT_ULL()/GENMASK()/etc) and helpers
(for_each_set_bit()/etc) where it makes sense.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: default avatarQiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent a50cc8de

drivers/edac/pnd2_edac.c

+14 −18
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ static int _apl_rd_reg(int port, int off, int op, u32 *data) 
	}



	P2SB_READ(dword, P2SB_DATA_OFF, data);

	ret = (status >> 1) & 0x3;

	ret = (status >> 1) & GENMASK(1, 0);

out:

	/* Hide the P2SB device, if it was hidden before */

	if (hidden)
@@ -307,7 +307,7 @@ static bool two_channels; /* Both PMI channels in one slice enabled */ 


static u8 sym_chan_mask;

static u8 asym_chan_mask;

static u8 chan_mask;

static unsigned long chan_mask;



static int slice_selector = -1;

static int chan_selector = -1;
@@ -598,7 +598,7 @@ static void remove_addr_bit(u64 *addr, int bitidx) 
	if (bitidx == -1)

		return;



	mask = (1ull << bitidx) - 1;

	mask = BIT_ULL(bitidx) - 1;

	*addr = ((*addr >> 1) & ~mask) | (*addr & mask);

}
@@ -642,7 +642,7 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg) 
	int sym_chan_shift = sym_channels >> 1;



	/* Give up if address is out of range, or in MMIO gap */

	if (addr >= (1ul << PND_MAX_PHYS_BIT) ||

	if (addr >= BIT(PND_MAX_PHYS_BIT) ||

	   (addr >= top_lm && addr < SZ_4G) || addr >= top_hm) {

		snprintf(msg, PND2_MSG_SIZE, "Error address 0x%llx is not DRAM", addr);

		return -EINVAL;
@@ -727,10 +727,10 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg) 
}



/* Translate PMI address to memory (rank, row, bank, column) */

#define C(n) (0x10 | (n))	/* column */

#define B(n) (0x20 | (n))	/* bank */

#define R(n) (0x40 | (n))	/* row */

#define RS   (0x80)			/* rank */

#define C(n) (BIT(4) | (n))	/* column */

#define B(n) (BIT(5) | (n))	/* bank */

#define R(n) (BIT(6) | (n))	/* row */

#define RS   (BIT(7))		/* rank */



/* addrdec values */

#define AMAP_1KB	0
@@ -1064,9 +1064,9 @@ static int apl_check_ecc_active(void) 
	int	i, ret = 0;



	/* Check dramtype and ECC mode for each present DIMM */

	for (i = 0; i < APL_NUM_CHANNELS; i++)

		if (chan_mask & BIT(i))

	for_each_set_bit(i, &chan_mask, APL_NUM_CHANNELS)

		ret += check_channel(i);



	return ret ? -EINVAL : 0;

}
@@ -1205,10 +1205,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) 
	u64	capacity;

	int	i, g;



	for (i = 0; i < APL_NUM_CHANNELS; i++) {

		if (!(chan_mask & BIT(i)))

			continue;



	for_each_set_bit(i, &chan_mask, APL_NUM_CHANNELS) {

		dimm = edac_get_dimm(mci, i, 0, 0);

		if (!dimm) {

			edac_dbg(0, "No allocated DIMM for channel %d\n", i);
@@ -1228,8 +1225,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) 
		}



		pvt->dimm_geom[i] = g;

		capacity = (d->rken0 + d->rken1) * 8 * (1ul << dimms[g].rowbits) *

				   (1ul << dimms[g].colbits);

		capacity = (d->rken0 + d->rken1) * 8 * BIT(dimms[g].rowbits + dimms[g].colbits);

		edac_dbg(0, "Channel %d: %lld MByte DIMM\n", i, capacity >> (20 - 3));

		dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));

		dimm->grain = 32;
@@ -1295,7 +1291,7 @@ static void dnv_get_dimm_config(struct mem_ctl_info *mci) 
				continue;

			}



			capacity = ranks_of_dimm[j] * banks * (1ul << rowbits) * (1ul << colbits);

			capacity = ranks_of_dimm[j] * banks * BIT(rowbits + colbits);

			edac_dbg(0, "Channel %d DIMM %d: %lld MByte DIMM\n", i, j, capacity >> (20 - 3));

			dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));

			dimm->grain = 32;