Commit 532e2c87 authored by Lancelot Six's avatar Lancelot Six Committed by Alex Deucher
Browse files

drm/amdkfd: Do not include VGPR MSBs in saved PC during save 



The current trap handler uses the top bits of ttmp1 to store a copy of
sq_wave_mode.*vgpr_msb (except for src2_vgpr_msb).  This is so the
effective values in sq_wave_mode can be cleared to ensure correct
behavior of the trap handler.

When saving sq_wave_mode, the trap handler correctly rebuilds the
expected value (with *vgpr_msb restored), so the save area is correct.
However, the PC itself is copied from ttmp[0:1], which contains the
wave's PC as well as the saved MSBs.

The debugger reads the PC from the save area and is confused when non-0
values from VGPR_MSBs are present.

This patch fixes this by saving the PC in the save area's PC slot, not
the composite of the PC and VGPR_MSBs.  On restore, the VGPR_MSBs are
restored from sq_wave_mode.

Signed-off-by: default avatarLancelot Six <lancelot.six@amd.com>
Tested-by: default avatarAlexey Kondratiev <Alexey.Kondratiev@amd.com>
Reviewed-by: default avatarJay Cornwall <jay.cornwall@amd.com>
Cc: Vladimir Indic <vladimir.indic@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf818707

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h

+3 −3
Original line number Diff line number Diff line
@@ -3760,8 +3760,8 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 
	0xb8faf804, 0x8b7a847a,

	0x91788478, 0x8c787a78,

	0xd7610002, 0x0000fa6c,

	0x807d817d, 0x917aff6d,

	0x80000000, 0xd7610002,

	0x807d817d, 0x8b7aff6d,

	0x0000ffff, 0xd7610002,

	0x0000fa7a, 0x807d817d,

	0xd7610002, 0x0000fa6e,

	0x807d817d, 0xd7610002,
@@ -4848,7 +4848,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 
	0x9178ff78, 0x0001000c,

	0x8c787a78, 0xd7610002,

	0x0000fa6c, 0x807d817d,

	0x917aff6d, 0x80000000,

	0x8b7aff6d, 0x01ffffff,

	0xd7610002, 0x0000fa7a,

	0x807d817d, 0xd7610002,

	0x0000fa6e, 0x807d817d,

drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ L_SAVE_HWREG: 
	s_or_b32	s_save_state_priv, s_save_state_priv, s_save_tmp



	write_hwreg_to_v2(s_save_pc_lo)

	s_andn2_b32	s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK

	s_and_b32       s_save_tmp, s_save_pc_hi, ADDRESS_HI32_MASK

	write_hwreg_to_v2(s_save_tmp)

	write_hwreg_to_v2(s_save_exec_lo)

#if WAVE32_ONLY