Commit 535677e9 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a09g077: Add CANFD clocks 



The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a CANFD
peripheral which has three input clocks PCLKM (peripheral clock),
PCLKH (RAM clock) and PCLKCAN (CANFD clock).

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224165049.3384870-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c07dd5ac

drivers/clk/renesas/r9a09g077-cpg.c

+12 −1
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#define FSELXSPI1	CONF_PACK(SCKCR, 8, 3)

#define DIVSEL_XSPI0	CONF_PACK(SCKCR, 6, 1)

#define DIVSEL_XSPI1	CONF_PACK(SCKCR, 14, 1)

#define FSELCANFD	CONF_PACK(SCKCR, 20, 1)

#define SEL_PLL		CONF_PACK(SCKCR, 22, 1)



#define DIVCA55C0	CONF_PACK(SCKCR2, 8, 1)
@@ -85,7 +86,7 @@ enum rzt2h_clk_types { 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,

	LAST_DT_CORE_CLK = R9A09G077_PCLKCAN,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -103,6 +104,9 @@ enum clk_ids { 
	CLK_PLL4D1,

	CLK_PLL4D1_DIV3,

	CLK_PLL4D1_DIV4,

	CLK_PLL4D3,

	CLK_PLL4D3_DIV10,

	CLK_PLL4D3_DIV20,

	CLK_SCI0ASYNC,

	CLK_SCI1ASYNC,

	CLK_SCI2ASYNC,
@@ -150,6 +154,7 @@ static const char * const sel_clk_pll1[] = { ".loco", ".pll1" }; 
static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };

static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };

static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" };

static const char * const sel_clk_pll4d3_div10_div20[] = { ".pll4d3_div10", ".pll4d3_div20" };



static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {

	/* External Clock Inputs */
@@ -174,6 +179,9 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { 
	DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),

	DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),

	DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),

	DEF_FIXED(".pll4d3", CLK_PLL4D3, CLK_SEL_CLK_PLL4, 3, 1),

	DEF_FIXED(".pll4d3_div10", CLK_PLL4D3_DIV10, CLK_PLL4D3, 10, 1),

	DEF_FIXED(".pll4d3_div20", CLK_PLL4D3_DIV20, CLK_PLL4D3, 20, 1),



	DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,

		dtable_24_25_30_32),
@@ -232,6 +240,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { 
			 FSELXSPI0, dtable_6_8_16_32_64),

	DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,

			 FSELXSPI1, dtable_6_8_16_32_64),

	DEF_MUX("PCLKCAN", R9A09G077_PCLKCAN, FSELCANFD,

		sel_clk_pll4d3_div10_div20, ARRAY_SIZE(sel_clk_pll4d3_div10_div20), 0),

};



static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
@@ -251,6 +261,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { 
	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),

	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),

	DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL),

	DEF_MOD("canfd", 310, R9A09G077_CLK_PCLKM),

	DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),