Commit 5359da47 authored by Qiang Yu's avatar Qiang Yu Committed by Vinod Koul
Browse files

phy: qcom-qmp: qserdes-txrx: Add complete QMP PCIe PHY v8 register offsets 



Kaanapali SoC uses QMP PHY with version v8 for PCIe Gen3 x2, but requires
a completely unique qserdes-txrx register offsets compared to existing v8
offsets.

Hence, add a dedicated header file containing the FULL SET of qserdes-txrx
register definitions required for Kaanapali's PCIe PHY operation.

Signed-off-by: default avatarJingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: default avatarQiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-2-d04ee9cca83b@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 4968df19

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-pcie-v8.h

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+71 −0
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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V8_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V8_H_



#define QSERDES_V8_PCIE_TX_RES_CODE_LANE_OFFSET_TX		0x030

#define QSERDES_V8_PCIE_TX_RES_CODE_LANE_OFFSET_RX		0x034

#define QSERDES_V8_PCIE_TX_LANE_MODE_1		0x07c

#define QSERDES_V8_PCIE_TX_LANE_MODE_2		0x080

#define QSERDES_V8_PCIE_TX_LANE_MODE_3		0x084

#define QSERDES_V8_PCIE_TX_TRAN_DRVR_EMP_EN		0x0b4

#define QSERDES_V8_PCIE_TX_TX_BAND0		0x0e0

#define QSERDES_V8_PCIE_TX_TX_BAND1		0x0e4

#define QSERDES_V8_PCIE_TX_SEL_10B_8B		0x0f4

#define QSERDES_V8_PCIE_TX_SEL_20B_10B		0x0f8

#define QSERDES_V8_PCIE_TX_PARRATE_REC_DETECT_IDLE_EN		0x058

#define QSERDES_V8_PCIE_TX_TX_ADAPT_POST_THRESH1		0x118

#define QSERDES_V8_PCIE_TX_TX_ADAPT_POST_THRESH2		0x11c

#define QSERDES_V8_PCIE_TX_PHPRE_CTRL		0x128

#define QSERDES_V8_PCIE_TX_EQ_RCF_CTRL_RATE3		0x148

#define QSERDES_V8_PCIE_TX_EQ_RCF_CTRL_RATE4		0x14c



#define QSERDES_V8_PCIE_RX_UCDR_FO_GAIN_RATE4		0x0dc

#define QSERDES_V8_PCIE_RX_UCDR_SO_GAIN_RATE3		0x0ec

#define QSERDES_V8_PCIE_RX_UCDR_SO_GAIN_RATE4		0x0f0

#define QSERDES_V8_PCIE_RX_UCDR_PI_CONTROLS		0x0f4

#define QSERDES_V8_PCIE_RX_VGA_CAL_CNTRL1		0x170

#define QSERDES_V8_PCIE_RX_VGA_CAL_MAN_VAL		0x178

#define QSERDES_V8_PCIE_RX_RX_EQU_ADAPTOR_CNTRL4		0x1b4

#define QSERDES_V8_PCIE_RX_SIGDET_ENABLES			0x1d8

#define QSERDES_V8_PCIE_RX_SIGDET_LVL			0x1e0

#define QSERDES_V8_PCIE_RX_RXCLK_DIV2_CTRL			0x0b8

#define QSERDES_V8_PCIE_RX_RX_BAND_CTRL0			0x0bc

#define QSERDES_V8_PCIE_RX_RX_TERM_BW_CTRL0			0x0c4

#define QSERDES_V8_PCIE_RX_RX_TERM_BW_CTRL1			0x0c8

#define QSERDES_V8_PCIE_RX_SVS_MODE_CTRL			0x0b4

#define QSERDES_V8_PCIE_RX_UCDR_PI_CTRL1			0x058

#define QSERDES_V8_PCIE_RX_UCDR_PI_CTRL2			0x05c

#define QSERDES_V8_PCIE_RX_UCDR_SB2_THRESH2_RATE3			0x084

#define QSERDES_V8_PCIE_RX_UCDR_SB2_GAIN1_RATE3			0x098

#define QSERDES_V8_PCIE_RX_UCDR_SB2_GAIN2_RATE3			0x0ac

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B0			0x218

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B1			0x21c

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B2			0x220

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B4			0x228

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE_0_1_B7			0x234

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B0			0x260

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B1			0x264

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B2			0x268

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B3			0x26c

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE3_B4			0x270

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B0			0x284

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B1			0x288

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B2			0x28c

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B3			0x290

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B4			0x294

#define QSERDES_V8_PCIE_RX_RX_MODE_RATE4_SA_B5			0x298

#define QSERDES_V8_PCIE_RX_Q_PI_INTRINSIC_BIAS_RATE32			0x31c

#define QSERDES_V8_PCIE_RX_Q_PI_INTRINSIC_BIAS_RATE4			0x320

#define QSERDES_V8_PCIE_RX_EOM_MAX_ERR_LIMIT_LSB			0x11c

#define QSERDES_V8_PCIE_RX_EOM_MAX_ERR_LIMIT_MSB			0x120

#define QSERDES_V8_PCIE_RX_AUXDATA_BIN_RATE23			0x108

#define QSERDES_V8_PCIE_RX_AUXDATA_BIN_RATE4			0x10c

#define QSERDES_V8_PCIE_RX_VTHRESH_CAL_MAN_VAL_RATE3			0x198

#define QSERDES_V8_PCIE_RX_VTHRESH_CAL_MAN_VAL_RATE4			0x19c

#define QSERDES_V8_PCIE_RX_GM_CAL			0x1a0



#endif