Commit 5363b67a authored by Xianwei Zhao's avatar Xianwei Zhao Committed by Thomas Gleixner
Browse files

irqchip/meson-gpio: Use the correct register in meson_s4_gpio_irq_set_type() 



meson_s4_gpio_irq_set_type() uses the both-edge trigger register for
configuring level type and single edge mode interrupts, which is not
correct.

Use REG_EDGE_POL instead.

Fixes: bbd6fcc7 ("irqchip: Add support for Amlogic A4 and A5 SoCs")
Signed-off-by: default avatarXianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: default avatarThomas Gleixner <tglx@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-1-9dc5f3e022e0@amlogic.com
parent 0fa10fb7

drivers/irqchip/irq-meson-gpio.c

+1 −2
Original line number Diff line number Diff line
@@ -415,8 +415,7 @@ static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, 
	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))

		val |= BIT(ctl->params->edge_single_offset + idx);



	meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,

				   BIT(idx) | BIT(12 + idx), val);

	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(idx) | BIT(12 + idx), val);

	return 0;

};