Commit 5390130f authored by Tero Kristo's avatar Tero Kristo Committed by Tony Lindgren
Browse files

ARM: dts: dra7: add timer_sys_ck entries for IPU/DSP timers 



With this, the clocksource driver can setup the timers properly.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 7cf0bb80

arch/arm/boot/dts/dra7-l4.dtsi

+26 −24
Original line number Diff line number Diff line
@@ -1163,8 +1163,8 @@ target-module@32000 { /* 0x48032000, ap 5 3e.0 */ 
			timer2: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -1191,8 +1191,8 @@ target-module@34000 { /* 0x48034000, ap 7 46.0 */ 
			timer3: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -1210,8 +1210,9 @@ target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 
					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			/* Domains (P, C): l4per_pwrdm, l4per_clkdm */

			clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;

			clock-names = "fck";

			clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>,

				 <&timer_sys_clk_div>;

			clock-names = "fck", "timer_sys_ck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x36000 0x1000>;
@@ -1219,8 +1220,8 @@ target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 
			timer4: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -1246,8 +1247,8 @@ target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ 
			timer9: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -1853,8 +1854,8 @@ target-module@86000 { /* 0x48086000, ap 41 5e.0 */ 
			timer10: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -1880,8 +1881,8 @@ target-module@88000 { /* 0x48088000, ap 43 66.0 */ 
			timer11: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -3354,8 +3355,8 @@ target-module@20000 { /* 0x48820000, ap 5 08.0 */ 
					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			/* Domains (P, C): ipu_pwrdm, ipu_clkdm */

			clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;

			clock-names = "fck";

			clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>;

			clock-names = "fck", "timer_sys_ck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x20000 0x1000>;
@@ -3381,8 +3382,9 @@ target-module@22000 { /* 0x48822000, ap 7 24.0 */ 
					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			/* Domains (P, C): ipu_pwrdm, ipu_clkdm */

			clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;

			clock-names = "fck";

			clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>,

				 <&timer_sys_clk_div>;

			clock-names = "fck", "timer_sys_ck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x22000 0x1000>;
@@ -3417,8 +3419,8 @@ target-module@24000 { /* 0x48824000, ap 9 26.0 */ 
			timer7: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -3444,8 +3446,8 @@ target-module@26000 { /* 0x48826000, ap 11 0c.0 */ 
			timer8: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

			};

		};
@@ -3471,8 +3473,8 @@ target-module@28000 { /* 0x48828000, ap 13 16.0 */ 
			timer13: timer@0 {

				compatible = "ti,omap5430-timer";

				reg = <0x0 0x80>;

				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;

				clock-names = "fck";

				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;

				clock-names = "fck", "timer_sys_ck";

				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;

				ti,timer-pwm;

			};