Commit 53bc516a authored by Pawan Gupta's avatar Pawan Gupta Committed by Borislav Petkov (AMD)
Browse files

x86/msr: Move ARCH_CAP_XAPIC_DISABLE bit definition to its rightful place 



The ARCH_CAP_XAPIC_DISABLE bit of MSR_IA32_ARCH_CAP is not in the
correct sorted order. Move it where it belongs.

No functional change.

  [ bp: Massage commit message. ]

Signed-off-by: default avatarPawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/243317ff6c8db307b7701a45f71e5c21da80194b.1705632532.git.pawan.kumar.gupta@linux.intel.com
parent e0ca9353

arch/x86/include/asm/msr-index.h

+4 −5
Original line number Diff line number Diff line
@@ -163,6 +163,10 @@ 
						 * are restricted to targets in

						 * kernel.

						 */

#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR

						 * supported

						 */

#define ARCH_CAP_PBRSB_NO		BIT(24)	/*

						 * Not susceptible to Post-Barrier

						 * Return Stack Buffer Predictions.
@@ -185,11 +189,6 @@ 
						 * File.

						 */



#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*

						 * IA32_XAPIC_DISABLE_STATUS MSR

						 * supported

						 */



#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			BIT(0)	/*

						 * Writeback and invalidate the