Commit 53d5abe6 authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Dmitry Baryshkov
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drm/msm/dpu: add CDM related logic to dpu_hw_ctl layer 



CDM block will need its own logic to program the flush and active
bits in the dpu_hw_ctl layer.

Make necessary changes in dpu_hw_ctl to support CDM programming.

changes in v3:
	- drop unused cdm_active as reported by kbot
	- retained the R-b as its a trivial change

changes in v2:
	- remove unused empty line
	- pass in cdm_num to update_pending_flush_cdm()

Reported-by: default avatarkernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202312102047.S0I69pCs-lkp@intel.com/


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/571829/
Link: https://lore.kernel.org/r/20231212205254.12422-11-quic_abhinavk@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 5ef42da7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+33 −0
Original line number Diff line number Diff line
@@ -32,11 +32,13 @@ 
#define   CTL_DSC_ACTIVE                0x0E8

#define   CTL_WB_ACTIVE                 0x0EC

#define   CTL_INTF_ACTIVE               0x0F4

#define   CTL_CDM_ACTIVE                0x0F8

#define   CTL_FETCH_PIPE_ACTIVE         0x0FC

#define   CTL_MERGE_3D_FLUSH            0x100

#define   CTL_DSC_FLUSH                0x104

#define   CTL_WB_FLUSH                  0x108

#define   CTL_INTF_FLUSH                0x110

#define   CTL_CDM_FLUSH                0x114

#define   CTL_INTF_MASTER               0x134

#define   CTL_DSPP_n_FLUSH(n)           ((0x13C) + ((n) * 4))
@@ -46,6 +48,7 @@ 
#define DPU_REG_RESET_TIMEOUT_US        2000

#define  MERGE_3D_IDX   23

#define  DSC_IDX        22

#define CDM_IDX         26

#define  INTF_IDX       31

#define WB_IDX          16

#define  DSPP_IDX       29  /* From DPU hw rev 7.x.x */
@@ -107,6 +110,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) 
	ctx->pending_wb_flush_mask = 0;

	ctx->pending_merge_3d_flush_mask = 0;

	ctx->pending_dsc_flush_mask = 0;

	ctx->pending_cdm_flush_mask = 0;



	memset(ctx->pending_dspp_flush_mask, 0,

		sizeof(ctx->pending_dspp_flush_mask));
@@ -151,6 +155,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) 
		DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,

			      ctx->pending_dsc_flush_mask);



	if (ctx->pending_flush_mask & BIT(CDM_IDX))

		DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH,

			      ctx->pending_cdm_flush_mask);



	DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);

}
@@ -282,6 +290,13 @@ static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx, 
	}

}



static void dpu_hw_ctl_update_pending_flush_cdm(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)

{

	/* update pending flush only if CDM_0 is flushed */

	if (cdm_num == CDM_0)

		ctx->pending_flush_mask |= BIT(CDM_IDX);

}



static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx,

		enum dpu_wb wb)

{
@@ -310,6 +325,12 @@ static void dpu_hw_ctl_update_pending_flush_dsc_v1(struct dpu_hw_ctl *ctx, 
	ctx->pending_flush_mask |= BIT(DSC_IDX);

}



static void dpu_hw_ctl_update_pending_flush_cdm_v1(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num)

{

	ctx->pending_cdm_flush_mask |= BIT(cdm_num - CDM_0);

	ctx->pending_flush_mask |= BIT(CDM_IDX);

}



static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,

	enum dpu_dspp dspp, u32 dspp_sub_blk)

{
@@ -543,6 +564,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, 


	if (cfg->dsc)

		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);



	if (cfg->cdm)

		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);

}



static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
@@ -586,6 +610,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
	u32 wb_active = 0;

	u32 merge3d_active = 0;

	u32 dsc_active;

	u32 cdm_active;



	/*

	 * This API resets each portion of the CTL path namely,
@@ -621,6 +646,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, 
		dsc_active &= ~cfg->dsc;

		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);

	}



	if (cfg->cdm) {

		cdm_active = DPU_REG_READ(c, CTL_CDM_ACTIVE);

		cdm_active &= ~cfg->cdm;

		DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);

	}

}



static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
@@ -654,12 +685,14 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, 
		ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;

		ops->update_pending_flush_dsc =

			dpu_hw_ctl_update_pending_flush_dsc_v1;

		ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;

	} else {

		ops->trigger_flush = dpu_hw_ctl_trigger_flush;

		ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;

		ops->update_pending_flush_intf =

			dpu_hw_ctl_update_pending_flush_intf;

		ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;

		ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;

	}

	ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;

	ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

+12 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct dpu_hw_stage_cfg { 
 * @mode_3d:               3d mux configuration

 * @merge_3d:              3d merge block used

 * @intf_mode_sel:         Interface mode, cmd / vid

 * @cdm:                   CDM block used

 * @stream_sel:            Stream selection for multi-stream interfaces

 * @dsc:                   DSC BIT masks used

 */
@@ -48,6 +49,7 @@ struct dpu_hw_intf_cfg { 
	enum dpu_3d_blend_mode mode_3d;

	enum dpu_merge_3d merge_3d;

	enum dpu_ctl_mode_sel intf_mode_sel;

	enum dpu_cdm cdm;

	int stream_sel;

	unsigned int dsc;

};
@@ -166,6 +168,14 @@ struct dpu_hw_ctl_ops { 
	void (*update_pending_flush_dsc)(struct dpu_hw_ctl *ctx,

					 enum dpu_dsc blk);



	/**

	 * OR in the given flushbits to the cached pending_(cdm_)flush_mask

	 * No effect on hardware

	 * @ctx: ctl path ctx pointer

	 * @cdm_num: idx of cdm to be flushed

	 */

	void (*update_pending_flush_cdm)(struct dpu_hw_ctl *ctx, enum dpu_cdm cdm_num);



	/**

	 * Write the value of the pending_flush_mask to hardware

	 * @ctx       : ctl path ctx pointer
@@ -239,6 +249,7 @@ struct dpu_hw_ctl_ops { 
 * @pending_intf_flush_mask: pending INTF flush

 * @pending_wb_flush_mask: pending WB flush

 * @pending_dsc_flush_mask: pending DSC flush

 * @pending_cdm_flush_mask: pending CDM flush

 * @ops: operation list

 */

struct dpu_hw_ctl {
@@ -256,6 +267,7 @@ struct dpu_hw_ctl { 
	u32 pending_merge_3d_flush_mask;

	u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0];

	u32 pending_dsc_flush_mask;

	u32 pending_cdm_flush_mask;



	/* ops */

	struct dpu_hw_ctl_ops ops;