Unverified Commit 53f4b30b authored by Kaustabh Chakraborty's avatar Kaustabh Chakraborty Committed by Inki Dae
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drm/exynos: exynos7_drm_decon: add driver data and support for Exynos7870 



Add support for Exynos 7870 DECON in the Exynos 7 DECON driver.

Some Exynos 7 series SoCs (Exynos 7580 onwards) have different
register values. In order to address such changes, include a driver
data struct (named decon_data) so that correct base addresses and
shift values can be provided.

Signed-off-by: default avatarKaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 5f1a4539

drivers/gpu/drm/exynos/exynos7_drm_decon.c

+44 −14
Original line number Diff line number Diff line
@@ -37,6 +37,24 @@ 


#define WINDOWS_NR	2



struct decon_data {

	unsigned int vidw_buf_start_base;

	unsigned int shadowcon_win_protect_shift;

	unsigned int wincon_burstlen_shift;

};



static struct decon_data exynos7_decon_data = {

	.vidw_buf_start_base = 0x80,

	.shadowcon_win_protect_shift = 10,

	.wincon_burstlen_shift = 11,

};



static struct decon_data exynos7870_decon_data = {

	.vidw_buf_start_base = 0x880,

	.shadowcon_win_protect_shift = 8,

	.wincon_burstlen_shift = 10,

};



struct decon_context {

	struct device			*dev;

	struct drm_device		*drm_dev;
@@ -55,11 +73,19 @@ struct decon_context { 
	wait_queue_head_t		wait_vsync_queue;

	atomic_t			wait_vsync_event;



	const struct decon_data *data;

	struct drm_encoder *encoder;

};



static const struct of_device_id decon_driver_dt_match[] = {

	{.compatible = "samsung,exynos7-decon"},

	{

		.compatible = "samsung,exynos7-decon",

		.data = &exynos7_decon_data,

	},

	{

		.compatible = "samsung,exynos7870-decon",

		.data = &exynos7870_decon_data,

	},

	{},

};

MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
@@ -92,8 +118,9 @@ static void decon_shadow_protect_win(struct decon_context *ctx, 
				     unsigned int win, bool protect)

{

	u32 bits, val;

	unsigned int shift = ctx->data->shadowcon_win_protect_shift;



	bits = SHADOWCON_WINx_PROTECT(win);

	bits = SHADOWCON_WINx_PROTECT(shift, win);



	val = readl(ctx->regs + SHADOWCON);

	if (protect)
@@ -291,6 +318,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 
{

	unsigned long val;

	int padding;

	unsigned int shift = ctx->data->wincon_burstlen_shift;



	val = readl(ctx->regs + WINCON(win));

	val &= ~WINCONx_BPPMODE_MASK;
@@ -298,44 +326,44 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 
	switch (fb->format->format) {

	case DRM_FORMAT_RGB565:

		val |= WINCONx_BPPMODE_16BPP_565;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_XRGB8888:

		val |= WINCONx_BPPMODE_24BPP_xRGB;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_XBGR8888:

		val |= WINCONx_BPPMODE_24BPP_xBGR;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_RGBX8888:

		val |= WINCONx_BPPMODE_24BPP_RGBx;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_BGRX8888:

		val |= WINCONx_BPPMODE_24BPP_BGRx;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_ARGB8888:

		val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_ABGR8888:

		val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_RGBA8888:

		val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	case DRM_FORMAT_BGRA8888:

	default:

		val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |

			WINCONx_ALPHA_SEL;

		val |= WINCONx_BURSTLEN_16WORD;

		val |= WINCONx_BURSTLEN_16WORD(shift);

		break;

	}
@@ -351,8 +379,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 


	padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;

	if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {

		val &= ~WINCONx_BURSTLEN_MASK;

		val |= WINCONx_BURSTLEN_8WORD;

		val &= ~WINCONx_BURSTLEN_MASK(shift);

		val |= WINCONx_BURSTLEN_8WORD(shift);

	}



	writel(val, ctx->regs + WINCON(win));
@@ -397,6 +425,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, 
	unsigned int win = plane->index;

	unsigned int cpp = fb->format->cpp[0];

	unsigned int pitch = fb->pitches[0];

	unsigned int vidw_addr0_base = ctx->data->vidw_buf_start_base;



	if (ctx->suspended)

		return;
@@ -413,7 +442,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, 


	/* buffer start address */

	val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);

	writel(val, ctx->regs + VIDW_BUF_START(win));

	writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win));



	padding = (pitch / cpp) - fb->width;
@@ -695,6 +724,7 @@ static int decon_probe(struct platform_device *pdev) 


	ctx->dev = dev;

	ctx->suspended = true;

	ctx->data = of_device_get_match_data(dev);



	i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");

	if (i80_if_timings)

drivers/gpu/drm/exynos/regs-decon7.h

+7 −8
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
/* SHADOWCON */

#define SHADOWCON				0x30



#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))

#define SHADOWCON_WINx_PROTECT(_shf, _win)	(1 << ((_shf) + (_win)))



/* WINCONx */

#define WINCON(_win)				(0x50 + ((_win) * 4))
@@ -58,10 +58,9 @@ 
#define WINCONx_BUFSEL_SHIFT			28

#define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)

#define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)

#define WINCONx_BURSTLEN_16WORD			(0x0 << 11)

#define WINCONx_BURSTLEN_8WORD			(0x1 << 11)

#define WINCONx_BURSTLEN_MASK			(0x1 << 11)

#define WINCONx_BURSTLEN_SHIFT			11

#define WINCONx_BURSTLEN_16WORD(_shf)		(0x0 << (_shf))

#define WINCONx_BURSTLEN_8WORD(_shf)		(0x1 << (_shf))

#define WINCONx_BURSTLEN_MASK(_shf)		(0x1 << (_shf))

#define WINCONx_BLD_PLANE			(0 << 8)

#define WINCONx_BLD_PIX				(1 << 8)

#define WINCONx_ALPHA_MUL			(1 << 7)
@@ -89,9 +88,9 @@ 
#define VIDOSD_H(_x)				(0x80 + ((_x) * 4))



/* Frame buffer start addresses: VIDWxxADD0n */

#define VIDW_BUF_START(_win)			(0x80 + ((_win) * 0x10))

#define VIDW_BUF_START1(_win)			(0x84 + ((_win) * 0x10))

#define VIDW_BUF_START2(_win)			(0x88 + ((_win) * 0x10))

#define VIDW_BUF_START(_base, _win)		((_base) + ((_win) * 0x10))

#define VIDW_BUF_START1(_base, _win)		((_base) + ((_win) * 0x10))

#define VIDW_BUF_START2(_base, _win)		((_base) + ((_win) * 0x10))



#define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))

#define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))