Commit 54377537 authored by Jian Hu's avatar Jian Hu Committed by Jerome Brunet
Browse files

dt-bindings: clock: add Amlogic T7 PLL clock controller 



Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.

Signed-off-by: default avatarJian Hu <jian.hu@amlogic.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20251212022619.3072132-2-jian.hu@amlogic.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 8f0b4cce

Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic T7 PLL Clock Control Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@amlogic.com>

  - Xianwei Zhao <xianwei.zhao@amlogic.com>



properties:

  compatible:

    enum:

      - amlogic,t7-gp0-pll

      - amlogic,t7-gp1-pll

      - amlogic,t7-hifi-pll

      - amlogic,t7-pcie-pll

      - amlogic,t7-mpll

      - amlogic,t7-hdmi-pll

      - amlogic,t7-mclk-pll



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: mclk pll input oscillator gate

      - description: oscillator input clock source for mclk_sel_0

      - description: fixed input clock source for mclk_sel_0

    minItems: 1



  clock-names:

    items:

      - const: in0

      - const: in1

      - const: in2

    minItems: 1



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: amlogic,t7-mclk-pll



    then:

      properties:

        clocks:

          minItems: 3



        clock-names:

          minItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - amlogic,t7-gp0-pll

              - amlogic,t7-gp1--pll

              - amlogic,t7-hifi-pll

              - amlogic,t7-pcie-pll

              - amlogic,t7-mpll

              - amlogic,t7-hdmi-pll



    then:

      properties:

        clocks:

          maxItems: 1



        clock-names:

          maxItems: 1



additionalProperties: false



examples:

  - |

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@8080 {

            compatible = "amlogic,t7-gp0-pll";

            reg = <0 0x8080 0 0x20>;

            clocks = <&scmi_clk 2>;

            clock-names = "in0";

            #clock-cells = <1>;

        };



        clock-controller@8300 {

            compatible = "amlogic,t7-mclk-pll";

            reg = <0 0x8300 0 0x18>;

            clocks = <&scmi_clk 2>,

                     <&xtal>,

                     <&scmi_clk 31>;

            clock-names = "in0", "in1", "in2";

            #clock-cells = <1>;

        };

    };

include/dt-bindings/clock/amlogic,t7-pll-clkc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */

/*

 * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved

 */



#ifndef __T7_PLL_CLKC_H

#define __T7_PLL_CLKC_H



/* GP0 */

#define CLKID_GP0_PLL_DCO	0

#define CLKID_GP0_PLL		1



/* GP1 */

#define CLKID_GP1_PLL_DCO	0

#define CLKID_GP1_PLL		1



/* HIFI */

#define CLKID_HIFI_PLL_DCO	0

#define CLKID_HIFI_PLL		1



/* PCIE */

#define CLKID_PCIE_PLL_DCO	0

#define CLKID_PCIE_PLL_DCO_DIV2	1

#define CLKID_PCIE_PLL_OD	2

#define CLKID_PCIE_PLL		3



/* MPLL */

#define CLKID_MPLL_PREDIV	0

#define CLKID_MPLL0_DIV		1

#define CLKID_MPLL0		2

#define CLKID_MPLL1_DIV		3

#define CLKID_MPLL1		4

#define CLKID_MPLL2_DIV		5

#define CLKID_MPLL2		6

#define CLKID_MPLL3_DIV		7

#define CLKID_MPLL3		8



/* HDMI */

#define CLKID_HDMI_PLL_DCO	0

#define CLKID_HDMI_PLL_OD	1

#define CLKID_HDMI_PLL		2



/* MCLK */

#define CLKID_MCLK_PLL_DCO	0

#define CLKID_MCLK_PRE		1

#define CLKID_MCLK_PLL		2

#define CLKID_MCLK_0_SEL	3

#define CLKID_MCLK_0_DIV2	4

#define CLKID_MCLK_0_PRE	5

#define CLKID_MCLK_0		6

#define CLKID_MCLK_1_SEL	7

#define CLKID_MCLK_1_DIV2	8

#define CLKID_MCLK_1_PRE	9

#define CLKID_MCLK_1		10



#endif /* __T7_PLL_CLKC_H */