Commit 5448c155 authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Joerg Roedel
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iommupt: Add the Intel VT-d second stage page table format



The VT-d second stage format is almost the same as the x86 PAE format,
except the bit encodings in the PTE are different and a few new PTE
features, like force coherency are present.

Among all the formats it is unique in not having a designated present bit.

Comparing the performance of several operations to the existing version:

iommu_map()
   pgsz  ,avg new,old ns, min new,old ns  , min % (+ve is better)
     2^12,     53,66    ,      50,64      ,  21.21
     2^21,     59,70    ,      56,67      ,  16.16
     2^30,     54,66    ,      52,63      ,  17.17
 256*2^12,    384,524   ,     337,516     ,  34.34
 256*2^21,    387,632   ,     336,626     ,  46.46
 256*2^30,    376,629   ,     323,623     ,  48.48

iommu_unmap()
   pgsz  ,avg new,old ns, min new,old ns  , min % (+ve is better)
     2^12,     67,86    ,      63,84      ,  25.25
     2^21,     64,84    ,      59,80      ,  26.26
     2^30,     59,78    ,      56,74      ,  24.24
 256*2^12,    216,335   ,     198,317     ,  37.37
 256*2^21,    245,350   ,     232,344     ,  32.32
 256*2^30,    248,345   ,     226,339     ,  33.33

Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent efa03dab
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+1 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ CONFIG_GENERIC_PT=y
CONFIG_DEBUG_GENERIC_PT=y
CONFIG_IOMMU_PT=y
CONFIG_IOMMU_PT_AMDV1=y
CONFIG_IOMMU_PT_VTDSS=y
CONFIG_IOMMU_PT_X86_64=y
CONFIG_IOMMU_PT_KUNIT_TEST=y

+11 −0
Original line number Diff line number Diff line
@@ -42,6 +42,16 @@ config IOMMU_PT_AMDV1

	  Selected automatically by an IOMMU driver that uses this format.

config IOMMU_PT_VTDSS
       tristate "IOMMU page table for Intel VT-d Second Stage"
	depends on !GENERIC_ATOMIC64 # for cmpxchg64
	help
	  iommu_domain implementation for the Intel VT-d's 64 bit 3/4/5
	  level Second Stage page table. It is similar to the X86_64 format with
	  4K/2M/1G page sizes.

	  Selected automatically by an IOMMU driver that uses this format.

config IOMMU_PT_X86_64
	tristate "IOMMU page table for x86 64-bit, 4/5 levels"
	depends on !GENERIC_ATOMIC64 # for cmpxchg64
@@ -57,6 +67,7 @@ config IOMMU_PT_KUNIT_TEST
	depends on KUNIT
	depends on IOMMU_PT_AMDV1 || !IOMMU_PT_AMDV1
	depends on IOMMU_PT_X86_64 || !IOMMU_PT_X86_64
	depends on IOMMU_PT_VTDSS || !IOMMU_PT_VTDSS
	default KUNIT_ALL_TESTS
	help
	  Enable kunit tests for GENERIC_PT and IOMMU_PT that covers all the
+2 −0
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@@ -3,6 +3,8 @@
iommu_pt_fmt-$(CONFIG_IOMMU_PT_AMDV1) += amdv1
iommu_pt_fmt-$(CONFIG_IOMMUFD_TEST) += mock

iommu_pt_fmt-$(CONFIG_IOMMU_PT_VTDSS) += vtdss

iommu_pt_fmt-$(CONFIG_IOMMU_PT_X86_64) += x86_64

IOMMU_PT_KUNIT_TEST :=
+21 −0
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
 *
 */
#ifndef __GENERIC_PT_FMT_DEFS_VTDSS_H
#define __GENERIC_PT_FMT_DEFS_VTDSS_H

#include <linux/generic_pt/common.h>
#include <linux/types.h>

typedef u64 pt_vaddr_t;
typedef u64 pt_oaddr_t;

struct vtdss_pt_write_attrs {
	u64 descriptor_bits;
	gfp_t gfp;
};
#define pt_write_attrs vtdss_pt_write_attrs

#endif
+10 −0
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// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES
 */
#define PT_FMT vtdss
#define PT_SUPPORTED_FEATURES                                            \
	(BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_VTDSS_FORCE_COHERENCE) | \
	 BIT(PT_FEAT_VTDSS_FORCE_WRITEABLE) | BIT(PT_FEAT_DMA_INCOHERENT))

#include "iommu_template.h"
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