Commit 54493279 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-fixes-6.14' of... 

Merge tag 'samsung-clk-fixes-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-fixes

Pull Samsung clk driver fixes from Krzysztof Kozlowski:

 - Google GS101: Fix synchronous external abort during system suspend.
   The driver access registers not available for OS, although issue
   would not be visible in earlier kernels due to missing suspend
   support.

 - Tesla FSD: Correct PLL142XX lock time

* tag 'samsung-clk-fixes-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: update PLL locktime for PLL142XX used on FSD platform
  clk: samsung: gs101: fix synchronous external abort in samsung_clk_save()
parents b8501feb 53517a70

drivers/clk/samsung/clk-gs101.c

+0 −8
Original line number Diff line number Diff line
@@ -382,17 +382,9 @@ static const unsigned long cmu_top_clk_regs[] __initconst = { 
	EARLY_WAKEUP_DPU_DEST,

	EARLY_WAKEUP_CSIS_DEST,

	EARLY_WAKEUP_SW_TRIG_APM,

	EARLY_WAKEUP_SW_TRIG_APM_SET,

	EARLY_WAKEUP_SW_TRIG_APM_CLEAR,

	EARLY_WAKEUP_SW_TRIG_CLUSTER0,

	EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,

	EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,

	EARLY_WAKEUP_SW_TRIG_DPU,

	EARLY_WAKEUP_SW_TRIG_DPU_SET,

	EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,

	EARLY_WAKEUP_SW_TRIG_CSIS,

	EARLY_WAKEUP_SW_TRIG_CSIS_SET,

	EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,

	CLK_CON_MUX_MUX_CLKCMU_BO_BUS,

	CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,

	CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,

drivers/clk/samsung/clk-pll.c

+6 −1
Original line number Diff line number Diff line
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = { 
 */

/* Maximum lock time can be 270 * PDIV cycles */

#define PLL35XX_LOCK_FACTOR	(270)

#define PLL142XX_LOCK_FACTOR	(150)



#define PLL35XX_MDIV_MASK       (0x3FF)

#define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,6 +273,10 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, 
	}



	/* Set PLL lock time. */

	if (pll->type == pll_142xx)

		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,

			pll->lock_reg);

	else

		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,

			pll->lock_reg);