Commit 54615eda authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/adreno: Update generated headers 



This updates the GPU headers to latest from mesa, using gen_header.py
(which is used to generate headers at bulid time for mesa), rather than
headergen2 (which doesn't have proper support for A6XX vs A7XX register
variants).

Mostly just uninteresting churn, but there are a couple spots in a7xx
paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are
a7xx specific.

Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Acked-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/574880/
parent a7165277

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+44 −29
Original line number Diff line number Diff line
@@ -3,28 +3,20 @@ 


/* Autogenerated file, DO NOT EDIT manually!



This file was generated by the rules-ng-ng headergen tool in this git repository:

http://github.com/freedreno/envytools/

git clone https://github.com/freedreno/envytools.git

This file was generated by the rules-ng-ng gen_header.py tool in this git repository:

http://gitlab.freedesktop.org/mesa/mesa/

git clone https://gitlab.freedesktop.org/mesa/mesa.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2023-03-10 18:32:52)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2022-07-23 20:21:46)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  91929 bytes, from 2023-02-28 23:52:27)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  15434 bytes, from 2023-03-10 18:32:53)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  74995 bytes, from 2023-03-20 18:06:23)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113474 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149590 bytes, from 2023-02-14 19:37:12)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 198949 bytes, from 2023-03-20 18:06:23)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11404 bytes, from 2023-03-10 18:32:53)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   9055 bytes, from 2023-03-10 18:32:52)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2976 bytes, from 2023-03-10 18:32:52)



Copyright (C) 2013-2023 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)



- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml          (  91929 bytes, from Fri Jun  2 14:59:26 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml  (   1572 bytes, from Fri Jun  2 14:59:26 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml (  15434 bytes, from Fri Jun  2 14:59:26 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml    (  85691 bytes, from Fri Feb 16 09:49:01 2024)



Copyright (C) 2013-2024 by the following authors:

- Rob Clark <robdclark@gmail.com> Rob Clark

- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin



Permission is hereby granted, free of charge, to any person obtaining

a copy of this software and associated documentation files (the
@@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION

OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION

WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.



*/



#ifdef __KERNEL__

#include <linux/bug.h>

#define assert(x) BUG_ON(!(x))

#else

#include <assert.h>

#endif



#ifdef __cplusplus

#define __struct_cast(X)

#else

#define __struct_cast(X) (struct X)

#endif



enum a2xx_rb_dither_type {

	DITHER_PIXEL = 0,
@@ -1442,16 +1447,18 @@ static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT			0

static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)

{

	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;

}

#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK			0x000003e0

#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT			5

static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)

{

	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;

}



static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }

#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))



static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
@@ -1661,7 +1668,8 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 
#define A2XX_RB_COLOR_INFO_BASE__SHIFT				12

static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)

{

	return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;

}



#define REG_A2XX_RB_DEPTH_INFO					0x00002002
@@ -1675,7 +1683,8 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form 
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12

static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)

{

	return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;

}



#define REG_A2XX_A225_RB_COLOR_INFO3				0x00002005
@@ -2654,7 +2663,8 @@ static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 
#define A2XX_RB_COPY_DEST_PITCH__SHIFT				0

static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)

{

	return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;

}



#define REG_A2XX_RB_COPY_DEST_INFO				0x0000231b
@@ -3027,7 +3037,8 @@ static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 
#define A2XX_SQ_TEX_0_PITCH__SHIFT				22

static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)

{

	return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;

}

#define A2XX_SQ_TEX_0_TILED					0x80000000
@@ -3061,7 +3072,8 @@ static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 
#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT			12

static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)

{

	return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;

}



#define REG_A2XX_SQ_TEX_2					0x00000002
@@ -3229,8 +3241,11 @@ static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 
#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT			12

static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)

{

	return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;

}



#ifdef __cplusplus

#endif



#endif /* A2XX_XML */

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+76 −55
Original line number Diff line number Diff line
@@ -3,28 +3,20 @@ 


/* Autogenerated file, DO NOT EDIT manually!



This file was generated by the rules-ng-ng headergen tool in this git repository:

http://github.com/freedreno/envytools/

git clone https://github.com/freedreno/envytools.git

This file was generated by the rules-ng-ng gen_header.py tool in this git repository:

http://gitlab.freedesktop.org/mesa/mesa/

git clone https://gitlab.freedesktop.org/mesa/mesa.git



The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2023-03-10 18:32:52)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2022-07-23 20:21:46)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  91929 bytes, from 2023-02-28 23:52:27)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  15434 bytes, from 2023-03-10 18:32:53)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  74995 bytes, from 2023-03-20 18:06:23)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113474 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149590 bytes, from 2023-02-14 19:37:12)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 198949 bytes, from 2023-03-20 18:06:23)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11404 bytes, from 2023-03-10 18:32:53)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2022-08-02 16:38:43)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   9055 bytes, from 2023-03-10 18:32:52)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2976 bytes, from 2023-03-10 18:32:52)



Copyright (C) 2013-2022 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)



- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml          (  84323 bytes, from Wed Aug 23 10:39:39 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml  (   1572 bytes, from Fri Jun  2 14:59:26 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml (  15434 bytes, from Fri Jun  2 14:59:26 2023)

- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml    (  85691 bytes, from Fri Feb 16 09:49:01 2024)



Copyright (C) 2013-2024 by the following authors:

- Rob Clark <robdclark@gmail.com> Rob Clark

- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin



Permission is hereby granted, free of charge, to any person obtaining

a copy of this software and associated documentation files (the
@@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION

OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION

WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.



*/



#ifdef __KERNEL__

#include <linux/bug.h>

#define assert(x) BUG_ON(!(x))

#else

#include <assert.h>

#endif



#ifdef __cplusplus

#define __struct_cast(X)

#else

#define __struct_cast(X) (struct X)

#endif



enum a3xx_tile_mode {

	LINEAR = 0,
@@ -612,6 +617,7 @@ enum a3xx_tex_msaa { 
#define A3XX_INT0_CP_AHB_ERROR_HALT				0x00200000

#define A3XX_INT0_MISC_HANG_DETECT				0x01000000

#define A3XX_INT0_UCHE_OOB_ACCESS				0x02000000



#define REG_A3XX_RBBM_HW_VERSION				0x00000000



#define REG_A3XX_RBBM_HW_RELEASE				0x00000001
@@ -672,13 +678,9 @@ enum a3xx_tex_msaa { 
#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3			0x0000005a



#define REG_A3XX_RBBM_INT_SET_CMD				0x00000060



#define REG_A3XX_RBBM_INT_CLEAR_CMD				0x00000061



#define REG_A3XX_RBBM_INT_0_MASK				0x00000063



#define REG_A3XX_RBBM_INT_0_STATUS				0x00000064



#define REG_A3XX_RBBM_PERFCTR_CTL				0x00000080

#define A3XX_RBBM_PERFCTR_CTL_ENABLE				0x00000001
@@ -912,7 +914,7 @@ enum a3xx_tex_msaa { 


#define REG_A3XX_CP_PROTECT_STATUS				0x0000045f



static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }

#define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0))



static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
@@ -1167,7 +1169,8 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) 
#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT			4

static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)

{

	return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;

}

#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00001000

#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM			0x00002000
@@ -1218,7 +1221,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 
	return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;

}



static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }

#define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0))



static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }

#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
@@ -1267,7 +1270,8 @@ static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 
#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		17

static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)

{

	return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;

}



static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
@@ -1275,7 +1279,8 @@ static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT		4

static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)

{

	return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;

}



static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
@@ -1407,7 +1412,8 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 
#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14

static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)

{

	return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;

	assert(!(val & 0x3fff));

	return (((val >> 14)) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;

}



#define REG_A3XX_RB_COPY_DEST_BASE				0x000020ed
@@ -1415,7 +1421,8 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 
#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT			4

static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)

{

	return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;

}



#define REG_A3XX_RB_COPY_DEST_PITCH				0x000020ee
@@ -1423,7 +1430,8 @@ static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 
#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0

static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)

{

	return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;

}



#define REG_A3XX_RB_COPY_DEST_INFO				0x000020ef
@@ -1491,7 +1499,8 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form 
#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			11

static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)

{

	return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;

}



#define REG_A3XX_RB_DEPTH_PITCH					0x00002103
@@ -1499,7 +1508,8 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 
#define A3XX_RB_DEPTH_PITCH__SHIFT				0

static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)

{

	return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;

	assert(!(val & 0x7));

	return (((val >> 3)) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;

}



#define REG_A3XX_RB_STENCIL_CONTROL				0x00002104
@@ -1562,7 +1572,8 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v 
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		11

static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)

{

	return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;

}



#define REG_A3XX_RB_STENCIL_PITCH				0x00002107
@@ -1570,7 +1581,8 @@ static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 
#define A3XX_RB_STENCIL_PITCH__SHIFT				0

static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)

{

	return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;

	assert(!(val & 0x7));

	return (((val >> 3)) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;

}



#define REG_A3XX_RB_STENCILREFMASK				0x00002108
@@ -1877,7 +1889,7 @@ static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 
	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;

}



static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }

#define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) (0x0000220b + 0x2*(i0))



static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
@@ -1889,7 +1901,7 @@ static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 


#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG			0x00002214



static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }

#define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) (0x00002215 + 0x1*(i0))



static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
@@ -1965,7 +1977,7 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 


#define REG_A3XX_VFD_INDEX_OFFSET				0x00002245



static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }

#define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0))



static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }

#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
@@ -1997,7 +2009,7 @@ static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 


static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }



static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }

#define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0))



static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }

#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
@@ -2084,7 +2096,7 @@ static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 
	return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;

}



static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }

#define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0))



static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }

#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK			0x00000003
@@ -2184,7 +2196,7 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;

}



static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }

#define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0))



static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }

#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK			0x00000003
@@ -2392,7 +2404,7 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 
	return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;

}



static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }

#define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))



static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }

#define A3XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
@@ -2422,7 +2434,7 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 
	return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;

}



static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }

#define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0))



static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }

#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x0000007f
@@ -2477,7 +2489,8 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT	0

static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)

{

	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;

	assert(!(val & 0x7f));

	return (((val >> 7)) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;

}

#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK	0x00ffff00

#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT	8
@@ -2503,7 +2516,8 @@ static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5

static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)

{

	return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;

}



#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG				0x000022d8
@@ -2641,7 +2655,8 @@ static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5

static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)

{

	return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;

}



#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG				0x000022e6
@@ -2665,7 +2680,7 @@ static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 
	return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;

}



static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }

#define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0))



static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }

#define A3XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
@@ -2678,7 +2693,7 @@ static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 
#define A3XX_SP_FS_MRT_REG_SINT					0x00000400

#define A3XX_SP_FS_MRT_REG_UINT					0x00000800



static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }

#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0))



static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }

#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK		0x0000003f
@@ -2821,18 +2836,20 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 
#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT				0

static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)

{

	return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;

}

#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0

#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT				5

static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)

{

	return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;

	assert(!(val & 0x1f));

	return (((val >> 5)) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;

}



#define REG_A3XX_VSC_SIZE_ADDRESS				0x00000c02



static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }

#define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))



static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }

#define A3XX_VSC_PIPE_CONFIG_X__MASK				0x000003ff
@@ -2887,7 +2904,7 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000 


#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT			0x00000c8b



static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }

#define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0))



static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
@@ -3228,7 +3245,8 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT			0

static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)

{

	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;

}

#define A3XX_TEX_CONST_3_DEPTH__MASK				0x0ffe0000

#define A3XX_TEX_CONST_3_DEPTH__SHIFT				17
@@ -3240,8 +3258,11 @@ static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 
#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT			28

static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)

{

	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;

	assert(!(val & 0xfff));

	return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;

}



#ifdef __cplusplus

#endif



#endif /* A3XX_XML */

drivers/gpu/drm/msm/adreno/a4xx.xml.h

+100 −82

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/a5xx.xml.h

+370 −296

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/a6xx.xml.h

+4434 −841

File changed.

Preview size limit exceeded, changes collapsed.