Commit 54647cd0 authored by Chuanhong Guo's avatar Chuanhong Guo Committed by Miquel Raynal
Browse files

mtd: spinand: gigadevice: add support for GD5FxGM7xExxG 



Add support for:
 GD5F{1,2}GM7{U,R}ExxG
 GD5F4GM8{U,R}ExxG

These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
with 8b/512b on-die ECC capability.
These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
instruction for reading page cache. It isn't added in this patch because
I don't have a DTR spi controller for testing.

Signed-off-by: default avatarChuanhong Guo <gch981213@gmail.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com
parent 194ec04b

drivers/mtd/nand/spi/gigadevice.c

+60 −0
Original line number Diff line number Diff line
@@ -441,6 +441,66 @@ static const struct spinand_info gigadevice_spinand_table[] = { 
		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq5xexxg_ecc_get_status)),

	SPINAND_INFO("GD5F1GM7UExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F1GM7RExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),

		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F2GM7UExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F2GM7RExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),

		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F4GM8UExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),

		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

	SPINAND_INFO("GD5F4GM8RExxG",

		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),

		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),

		     NAND_ECCREQ(8, 512),

		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,

					      &write_cache_variants,

					      &update_cache_variants),

		     SPINAND_HAS_QE_BIT,

		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,

				     gd5fxgq4uexxg_ecc_get_status)),

};



static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {