Commit 5485eb95 authored by Dan Williams's avatar Dan Williams
Browse files

Merge branch 'for-6.3/cxl' into cxl/next 

Merge the general CXL updates with fixes targeting v6.2-rc for v6.3.
Resolve a conflict with the fix and move of cxl_report_and_clear() from
pci.c to core/pci.c.
parents 711442e2 623c0751

Documentation/ABI/testing/sysfs-bus-cxl

+15 −0
Original line number Diff line number Diff line
@@ -90,6 +90,21 @@ Description: 
		capability.





What:		/sys/bus/cxl/devices/{port,endpoint}X/parent_dport

Date:		January, 2023

KernelVersion:	v6.3

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) CXL port objects are instantiated for each upstream port in

		a CXL/PCIe switch, and for each endpoint to map the

		corresponding memory device into the CXL port hierarchy. When a

		descendant CXL port (switch or endpoint) is enumerated it is

		useful to know which 'dport' object in the parent CXL port

		routes to this descendant. The 'parent_dport' symlink points to

		the device representing the downstream port of a CXL switch that

		routes to {port,endpoint}X.





What:		/sys/bus/cxl/devices/portX/dportY

Date:		June, 2021

KernelVersion:	v5.14

drivers/acpi/pci_root.c

+3 −0
Original line number Diff line number Diff line
@@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root, 
	if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))

		host_bridge->native_dpc = 0;



	if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))

		host_bridge->native_cxl_error = 0;



	/*

	 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it

	 * exists and returns 0, we must preserve any PCI resource

drivers/cxl/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ config CXL_REGION_INVALIDATION_TEST 
	depends on CXL_REGION

	help

	  CXL Region management and security operations potentially invalidate

	  the content of CPU caches without notifiying those caches to

	  the content of CPU caches without notifying those caches to

	  invalidate the affected cachelines. The CXL Region driver attempts

	  to invalidate caches when those events occur.  If that invalidation

	  fails the region will fail to enable.  Reasons for cache

drivers/cxl/acpi.c

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ struct cxl_cxims_data { 


/*

 * Find a targets entry (n) in the host bridge interleave list.

 * CXL Specfication 3.0 Table 9-22

 * CXL Specification 3.0 Table 9-22

 */

static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,

			  int ig)

drivers/cxl/core/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ obj-$(CONFIG_CXL_BUS) += cxl_core.o 
obj-$(CONFIG_CXL_SUSPEND) += suspend.o



ccflags-y += -I$(srctree)/drivers/cxl

CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src)



cxl_core-y := port.o

cxl_core-y += pmem.o

cxl_core-y += regs.o
@@ -10,4 +12,5 @@ cxl_core-y += memdev.o 
cxl_core-y += mbox.o

cxl_core-y += pci.o

cxl_core-y += hdm.o

cxl_core-$(CONFIG_TRACING) += trace.o

cxl_core-$(CONFIG_CXL_REGION) += region.o