Commit 549435aa authored by Yosry Ahmed's avatar Yosry Ahmed Committed by Ingo Molnar
Browse files

x86/bugs: Move the X86_FEATURE_USE_IBPB check into callers 



indirect_branch_prediction_barrier() only performs the MSR write if
X86_FEATURE_USE_IBPB is set, using alternative_msr_write(). In
preparation for removing X86_FEATURE_USE_IBPB, move the feature check
into the callers so that they can be addressed one-by-one, and use
X86_FEATURE_IBPB instead to guard the MSR write.

Signed-off-by: default avatarYosry Ahmed <yosry.ahmed@linux.dev>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Acked-by: default avatarJosh Poimboeuf <jpoimboe@kernel.org>
Acked-by: default avatarSean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20250227012712.3193063-2-yosry.ahmed@linux.dev
parent 8442df2b

arch/x86/include/asm/nospec-branch.h

+1 −1
Original line number Diff line number Diff line
@@ -515,7 +515,7 @@ extern u64 x86_pred_cmd; 


static inline void indirect_branch_prediction_barrier(void)

{

	alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);

	alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_IBPB);

}



/* The Intel SPEC CTRL MSR base value cache */

arch/x86/kernel/cpu/bugs.c

+1 −1
Original line number Diff line number Diff line
@@ -2272,7 +2272,7 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) 
		if (ctrl == PR_SPEC_FORCE_DISABLE)

			task_set_spec_ib_force_disable(task);

		task_update_spec_tif(task);

		if (task == current)

		if (task == current && cpu_feature_enabled(X86_FEATURE_USE_IBPB))

			indirect_branch_prediction_barrier();

		break;

	default:

arch/x86/kvm/svm/svm.c

+2 −1
Original line number Diff line number Diff line
@@ -1565,7 +1565,8 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 
	if (sd->current_vmcb != svm->vmcb) {

		sd->current_vmcb = svm->vmcb;



		if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT))

		if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT) &&

		    cpu_feature_enabled(X86_FEATURE_USE_IBPB))

			indirect_branch_prediction_barrier();

	}

	if (kvm_vcpu_apicv_active(vcpu))

arch/x86/kvm/vmx/nested.c

+2 −1
Original line number Diff line number Diff line
@@ -5026,7 +5026,8 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, 
	 * doesn't isolate different VMCSs, i.e. in this case, doesn't provide

	 * separate modes for L2 vs L1.

	 */

	if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL))

	if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) &&

	    cpu_feature_enabled(X86_FEATURE_USE_IBPB))

		indirect_branch_prediction_barrier();



	/* Update any VMCS fields that might have changed while L2 ran */

arch/x86/kvm/vmx/vmx.c

+2 −1
Original line number Diff line number Diff line
@@ -1477,7 +1477,8 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, 
		 * performs IBPB on nested VM-Exit (a single nested transition

		 * may switch the active VMCS multiple times).

		 */

		if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))

		if (cpu_feature_enabled(X86_FEATURE_USE_IBPB) &&

		    (!buddy || WARN_ON_ONCE(buddy->vmcs != prev)))

			indirect_branch_prediction_barrier();

	}