Commit 549f4ae2 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: rzg2l: Wait for status bit of SD mux before continuing 



The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.

Fixes: eaff3364 ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent d5252d96

drivers/clk/renesas/rzg2l-cpg.c

+10 −7
Original line number Diff line number Diff line
@@ -188,7 +188,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) 
	u32 off = GET_REG_OFFSET(hwdata->conf);

	u32 shift = GET_SHIFT(hwdata->conf);

	const u32 clk_src_266 = 2;

	u32 bitmask;

	u32 msk, val, bitmask;

	int ret;



	/*

	 * As per the HW manual, we should not directly switch from 533 MHz to
@@ -202,14 +203,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) 
	 * the index to value mapping is done by adding 1 to the index.

	 */

	bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;

	msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;

	if (index != clk_src_266) {

		u32 msk, val;

		int ret;



		writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);



		msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;



		ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,

					 !(val & msk), 100,

					 CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
@@ -221,7 +218,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) 


	writel(bitmask | ((index + 1) << shift), priv->base + off);



	return 0;

	ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,

				 !(val & msk), 100,

				 CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);

	if (ret)

		dev_err(priv->dev, "failed to switch clk source\n");



	return ret;

}



static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)