Commit 54a3cc14 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Remove extra ISBs when using msr_hcr_el2 



The msr_hcr_el2 macro is slightly awkward, as it provides an ISB
when CONFIG_AMPERE_ERRATUM_AC04_CPU_23 is present, and none
otherwise. Note that this this option is 'default y', meaning that
it is likely to be selected.

Most instances of msr_hcr_el2 are also immediately followed by an ISB,
meaning that in most cases, you end-up with two back-to-back ISBs.
This isn't a big deal, but once you have seen that, you can't unsee it.

Rework the msr_hcr_el2 macro to always provide the ISB, and drop
the superfluous ISBs everywhere else.

Reviewed-by: default avatarFuad Tabba <tabba@google.com>
Tested-by: default avatarFuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260321212419.2803972-6-maz@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 59c6e12d

arch/arm64/include/asm/el2_setup.h

+0 −2
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ 
	 * effectively VHE-only or not.

	 */

	msr_hcr_el2 x0		// Setup HCR_EL2 as nVHE

	isb

	mov	x1, #1		// Write something to FAR_EL1

	msr	far_el1, x1

	isb
@@ -64,7 +63,6 @@ 
.LnE2H0_\@:

	orr	x0, x0, #HCR_E2H

	msr_hcr_el2 x0

	isb

.LnVHE_\@:

.endm

arch/arm64/include/asm/sysreg.h

+2 −4
Original line number Diff line number Diff line
@@ -1114,11 +1114,9 @@ 
	.macro	msr_hcr_el2, reg

#if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23)

	dsb	nsh

	msr	hcr_el2, \reg

	isb

#else

	msr	hcr_el2, \reg

#endif

	msr	hcr_el2, \reg

	isb			// Required by AMPERE_ERRATUM_AC04_CPU_23

	.endm

#else

arch/arm64/kernel/hyp-stub.S

+0 −1
Original line number Diff line number Diff line
@@ -103,7 +103,6 @@ SYM_CODE_START_LOCAL(__finalise_el2) 
	// Engage the VHE magic!

	mov_q	x0, HCR_HOST_VHE_FLAGS

	msr_hcr_el2 x0

	isb



	// Use the EL1 allocated stack, per-cpu offset

	mrs	x0, sp_el1

arch/arm64/kvm/hyp/nvhe/host.S

+0 −1
Original line number Diff line number Diff line
@@ -125,7 +125,6 @@ SYM_FUNC_START(__hyp_do_panic) 
	mrs	x0, hcr_el2

	bic	x0, x0, #HCR_VM

	msr_hcr_el2 x0

	isb

	tlbi	vmalls12e1

	dsb	nsh

#endif