Commit 54c65966 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Michał Winiarski
Browse files

drm/xe: Make xe_mmio_read|write() functions non-inline 



Shortly we will updating xe_mmio_read|write() functions with SR-IOV
specific features making those functions less suitable for inline.
Convert now those functions into regular ones, lowering driver
footprint, according to scripts/bloat-o-meter, by 6%

add/remove: 18/18 grow/shrink: 31/603 up/down: 2719/-79663 (-76944)
Function                                     old     new   delta
Total: Before=1276633, After=1199689, chg -6.03%
add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
Data                                         old     new   delta
Total: Before=48990, After=48990, chg +0.00%
add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
RO Data                                      old     new   delta
Total: Before=115680, After=115680, chg +0.00%

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240314173130.1177-7-michal.wajdeczko@intel.com


Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
parent 42b266be

drivers/gpu/drm/xe/xe_mmio.c

+72 −0
Original line number Diff line number Diff line
@@ -420,6 +420,78 @@ int xe_mmio_root_tile_init(struct xe_device *xe) 
	return 0;

}



u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set)

{

	u32 old, reg_val;



	old = xe_mmio_read32(gt, reg);

	reg_val = (old & ~clr) | set;

	xe_mmio_write32(gt, reg, reg_val);



	return old;

}



int xe_mmio_write32_and_verify(struct xe_gt *gt,

			       struct xe_reg reg, u32 val, u32 mask, u32 eval)

{

	u32 reg_val;



	xe_mmio_write32(gt, reg, val);

	reg_val = xe_mmio_read32(gt, reg);



	return (reg_val & mask) != eval ? -EINVAL : 0;

}



bool xe_mmio_in_range(const struct xe_gt *gt,

		      const struct xe_mmio_range *range,

		      struct xe_reg reg)

{

	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return range && reg.addr >= range->start && reg.addr <= range->end;

}



/**

 * xe_mmio_read64_2x32() - Read a 64-bit register as two 32-bit reads

 * @gt: MMIO target GT

drivers/gpu/drm/xe/xe_mmio.h

+7 −74
Original line number Diff line number Diff line
@@ -24,80 +24,13 @@ int xe_mmio_init(struct xe_device *xe); 
int xe_mmio_root_tile_init(struct xe_device *xe);

void xe_mmio_probe_tiles(struct xe_device *xe);



static inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



static inline u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



static inline void xe_mmio_write32(struct xe_gt *gt,

				   struct xe_reg reg, u32 val)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



static inline u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

}



static inline u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr,

				u32 set)

{

	u32 old, reg_val;



	old = xe_mmio_read32(gt, reg);

	reg_val = (old & ~clr) | set;

	xe_mmio_write32(gt, reg, reg_val);



	return old;

}



static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,

					     struct xe_reg reg, u32 val,

					     u32 mask, u32 eval)

{

	u32 reg_val;



	xe_mmio_write32(gt, reg, val);

	reg_val = xe_mmio_read32(gt, reg);



	return (reg_val & mask) != eval ? -EINVAL : 0;

}



static inline bool xe_mmio_in_range(const struct xe_gt *gt,

				    const struct xe_mmio_range *range,

				    struct xe_reg reg)

{

	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return range && reg.addr >= range->start && reg.addr <= range->end;

}

u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg);

u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg);

void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);

u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg);

u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set);

int xe_mmio_write32_and_verify(struct xe_gt *gt, struct xe_reg reg, u32 val, u32 mask, u32 eval);

bool xe_mmio_in_range(const struct xe_gt *gt, const struct xe_mmio_range *range, struct xe_reg reg);



int xe_mmio_probe_vram(struct xe_device *xe);

u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg);