Commit 54cb3bb4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'riscv-sg2042-clk-for-v6.11' of https://github.com/sophgo/linux into clk-sophgo 

Pull RISC-V SG2042 clock driver changes from Chen Wang:

 - Add sg2042 clk driver

* tag 'riscv-sg2042-clk-for-v6.11' of https://github.com/sophgo/linux:
  clk: sophgo: Add SG2042 clock driver
  dt-bindings: clock: sophgo: add clkgen for SG2042
  dt-bindings: clock: sophgo: add RP gate clocks for SG2042
  dt-bindings: clock: sophgo: add pll clocks for SG2042
parents 1613e604 48cf7e01

Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 Clock Generator for divider/mux/gate



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-clkgen



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Main PLL

      - description: Fixed PLL

      - description: DDR PLL 0

      - description: DDR PLL 1



  clock-names:

    items:

      - const: mpll

      - const: fpll

      - const: dpll0

      - const: dpll1



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@30012000 {

      compatible = "sophgo,sg2042-clkgen";

      reg = <0x30012000 0x1000>;

      clocks = <&pllclk 0>,

               <&pllclk 1>,

               <&pllclk 2>,

               <&pllclk 3>;

      clock-names = "mpll",

                    "fpll",

                    "dpll0",

                    "dpll1";

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 PLL Clock Generator



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-pll



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)

      - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)

      - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)



  clock-names:

    items:

      - const: cgi_main

      - const: cgi_dpll0

      - const: cgi_dpll1



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@10000000 {

      compatible = "sophgo,sg2042-pll";

      reg = <0x10000000 0x10000>;

      clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;

      clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-rpgate



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Gate clock for RP subsystem



  clock-names:

    items:

      - const: rpgate



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@20000000 {

      compatible = "sophgo,sg2042-rpgate";

      reg = <0x20000000 0x10000>;

      clocks = <&clkgen 85>;

      clock-names = "rpgate";

      #clock-cells = <1>;

    };

drivers/clk/sophgo/Kconfig

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@@ -9,3 +9,31 @@ config CLK_SOPHGO_CV1800 
	  The driver require a 25MHz Oscillator to function generate clock.

	  It includes PLLs, common clock function and some vendor clock for

	  IPs of CV18XX series SoC



config CLK_SOPHGO_SG2042_PLL

	tristate "Sophgo SG2042 PLL clock support"

	depends on ARCH_SOPHGO || COMPILE_TEST

	help

	  This driver supports the PLL clock controller on the

	  Sophgo SG2042 SoC. This clock IP uses three oscillators with

	  frequency of 25 MHz as input, which are used for Main/Fixed

	  PLL, DDR PLL 0 and DDR PLL 1 respectively.



config CLK_SOPHGO_SG2042_CLKGEN

	tristate "Sophgo SG2042 Clock Generator support"

	depends on CLK_SOPHGO_SG2042_PLL

	help

	  This driver supports the Clock Generator on the

	  Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock

	  because it uses PLL clocks as input.

	  This driver provides clock function such as DIV/Mux/Gate.



config CLK_SOPHGO_SG2042_RPGATE

	tristate "Sophgo SG2042 RP subsystem clock controller support"

	depends on CLK_SOPHGO_SG2042_CLKGEN

	help

	  This driver supports the RP((Riscv Processors)) subsystem clock

	  controller on the Sophgo SG2042 SoC.

	  This clock IP depends on SG2042 Clock Generator because it uses

	  clock from Clock Generator IP as input.

	  This driver provides Gate function for RP.

drivers/clk/sophgo/Makefile

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@@ -5,3 +5,7 @@ clk-sophgo-cv1800-y += clk-cv1800.o 
clk-sophgo-cv1800-y		+= clk-cv18xx-common.o

clk-sophgo-cv1800-y		+= clk-cv18xx-ip.o

clk-sophgo-cv1800-y		+= clk-cv18xx-pll.o



obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN)	+= clk-sg2042-clkgen.o

obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL)	+= clk-sg2042-pll.o

obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE)	+= clk-sg2042-rpgate.o