Commit 5542b0b5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.14' of... 

Merge tag 'qcom-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Support for various Qualcomm clk controllers: IPQ CMN PLL, SM6115
   LPASS, SM750 global, tcsr, rpmh, and display. X Plus GPU and global.
   QCS615 rpmh and MSM8937 and MSM8940 RPM.
 - Support for Qualcomm Pongo and Taycan Alpha PLLs
 - Describe Qualcomm X Elite Titan GDSC relationships
 - Mark Qualcomm SM8550 and SM8650 PCIe GDSCs and X Elite USB GDSC as
   retention/on
 - Allow Qualcomm SDM845 general purpose clk to have arbitrary
   frequencies
 - Add Qualcomm IPQ5424 NoC-related interconnect clks

* tag 'qcom-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (63 commits)
  clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
  dt-bindings: clock: move qcom,x1e80100-camcc to its own file
  clk: qcom: smd-rpm: Add clocks for MSM8940
  dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
  clk: qcom: smd-rpm: Add clocks for MSM8937
  dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
  clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
  dt-bindings: interconnect: Add Qualcomm IPQ5424 support
  clk: qcom: Add SM6115 LPASSCC
  dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
  clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
  clk: qcom: gcc-sdm845: Add general purpose clock ops
  clk: qcom: clk-rcg2: split __clk_rcg2_configure function
  clk: qcom: clk-rcg2: document calc_rate function
  clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
  clk: qcom: ipq5424: add gcc_xo_clk
  dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
  dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
  clk: qcom: ipq5424: remove apss_dbg clock
  dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
  ...
parents 40384c84 5e419033

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm CMN PLL Clock Controller on IPQ SoC



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Luo Jie <quic_luoj@quicinc.com>



description:

  The CMN (or common) PLL clock controller expects a reference

  input clock. This reference clock is from the on-board Wi-Fi.

  The CMN PLL supplies a number of fixed rate output clocks to

  the devices providing networking functions and to GCC. These

  networking hardware include PPE (packet process engine), PCS

  and the externally connected switch or PHY devices. The CMN

  PLL block also outputs fixed rate clocks to GCC. The PLL's

  primary function is to enable fixed rate output clocks for

  networking hardware functions used with the IPQ SoC.



properties:

  compatible:

    enum:

      - qcom,ipq9574-cmn-pll



  reg:

    maxItems: 1



  clocks:

    items:

      - description: The reference clock. The supported clock rates include

          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.

      - description: The AHB clock

      - description: The SYS clock

    description:

      The reference clock is the source clock of CMN PLL, which is from the

      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL

      clock registers.



  clock-names:

    items:

      - const: ref

      - const: ahb

      - const: sys



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>

    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>



    cmn_pll: clock-controller@9b000 {

        compatible = "qcom,ipq9574-cmn-pll";

        reg = <0x0009b000 0x800>;

        clocks = <&cmn_pll_ref_clk>,

                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,

                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;

        clock-names = "ref", "ahb", "sys";

        #clock-cells = <1>;

        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;

        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;

    };

...

Documentation/devicetree/bindings/clock/qcom,mmcc.yaml

+4 −0
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@@ -78,6 +78,7 @@ allOf: 
    then:

      properties:

        clocks:

          minItems: 8

          items:

            - description: Board PXO source

            - description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf: 
            - description: DSI phy instance 2 dsi clock

            - description: DSI phy instance 2 byte clock

            - description: HDMI phy PLL clock

            - description: LVDS PLL clock



        clock-names:

          minItems: 8

          items:

            - const: pxo

            - const: pll3
@@ -98,6 +101,7 @@ allOf: 
            - const: dsi2pll

            - const: dsi2pllbyte

            - const: hdmipll

            - const: lvdspll



  - if:

      properties:

Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on QCS615



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on QCS615.



  See also: include/dt-bindings/clock/qcom,qcs615-gcc.h



properties:

  compatible:

    const: qcom,qcs615-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk



required:

  - compatible

  - clocks

  - clock-names

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,qcs615-gcc";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml

+4 −0
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@@ -33,6 +33,8 @@ properties: 
          - qcom,rpmcc-msm8916

          - qcom,rpmcc-msm8917

          - qcom,rpmcc-msm8936

          - qcom,rpmcc-msm8937

          - qcom,rpmcc-msm8940

          - qcom,rpmcc-msm8953

          - qcom,rpmcc-msm8974

          - qcom,rpmcc-msm8976
@@ -110,6 +112,8 @@ allOf: 
              - qcom,rpmcc-msm8916

              - qcom,rpmcc-msm8917

              - qcom,rpmcc-msm8936

              - qcom,rpmcc-msm8937

              - qcom,rpmcc-msm8940

              - qcom,rpmcc-msm8953

              - qcom,rpmcc-msm8974

              - qcom,rpmcc-msm8976

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -17,6 +17,7 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,qcs615-rpmh-clk

      - qcom,qdu1000-rpmh-clk

      - qcom,sa8775p-rpmh-clk

      - qcom,sar2130p-rpmh-clk
@@ -37,6 +38,7 @@ properties: 
      - qcom,sm8450-rpmh-clk

      - qcom,sm8550-rpmh-clk

      - qcom,sm8650-rpmh-clk

      - qcom,sm8750-rpmh-clk

      - qcom,x1e80100-rpmh-clk



  clocks: