Commit 5543604a authored by Qin Jian's avatar Qin Jian Committed by Arnd Bergmann
Browse files

dt-bindings: clock: Add bindings for SP7021 clock driver 



Add documentation to describe Sunplus SP7021 clock driver bindings.

Signed-off-by: default avatarQin Jian <qinjian@cqplus1.com>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent dbf018be

Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) Sunplus Co., Ltd. 2021

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sunplus SP7021 SoC Clock Controller



maintainers:

  - Qin Jian <qinjian@cqplus1.com>



properties:

  compatible:

    const: sunplus,sp7021-clkc



  reg:

    maxItems: 3



  clocks:

    maxItems: 1



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    extclk: osc0 {

      compatible = "fixed-clock";

      #clock-cells = <0>;

      clock-frequency = <27000000>;

      clock-output-names = "extclk";

    };



    clkc: clock-controller@9c000004 {

      compatible = "sunplus,sp7021-clkc";

      reg = <0x9c000004 0x28>,

            <0x9c000200 0x44>,

            <0x9c000268 0x08>;

      clocks = <&extclk>;

      #clock-cells = <1>;

    };



...

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -2831,8 +2831,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) 
S:	Maintained

W:	https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview

F:	Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml

F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml

F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml

F:	drivers/reset/reset-sunplus.c

F:	include/dt-bindings/clock/sunplus,sp7021-clkc.h

F:	include/dt-bindings/reset/sunplus,sp7021-reset.h









ARM/Synaptics SoC support
































include/dt-bindings/clock/sunplus,sp7021-clkc.h
0 → 100644



+88
−0






























Original line number
Diff line number
Diff line









/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */









/*









 * Copyright (C) Sunplus Technology Co., Ltd.









 *       All rights reserved.









 */









#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H









#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H



















/* gates */









#define CLK_RTC         0









#define CLK_OTPRX       1









#define CLK_NOC         2









#define CLK_BR          3









#define CLK_SPIFL       4









#define CLK_PERI0       5









#define CLK_PERI1       6









#define CLK_STC0        7









#define CLK_STC_AV0     8









#define CLK_STC_AV1     9









#define CLK_STC_AV2     10









#define CLK_UA0         11









#define CLK_UA1         12









#define CLK_UA2         13









#define CLK_UA3         14









#define CLK_UA4         15









#define CLK_HWUA        16









#define CLK_DDC0        17









#define CLK_UADMA       18









#define CLK_CBDMA0      19









#define CLK_CBDMA1      20









#define CLK_SPI_COMBO_0 21









#define CLK_SPI_COMBO_1 22









#define CLK_SPI_COMBO_2 23









#define CLK_SPI_COMBO_3 24









#define CLK_AUD         25









#define CLK_USBC0       26









#define CLK_USBC1       27









#define CLK_UPHY0       28









#define CLK_UPHY1       29









#define CLK_I2CM0       30









#define CLK_I2CM1       31









#define CLK_I2CM2       32









#define CLK_I2CM3       33









#define CLK_PMC         34









#define CLK_CARD_CTL0   35









#define CLK_CARD_CTL1   36









#define CLK_CARD_CTL4   37









#define CLK_BCH         38









#define CLK_DDFCH       39









#define CLK_CSIIW0      40









#define CLK_CSIIW1      41









#define CLK_MIPICSI0    42









#define CLK_MIPICSI1    43









#define CLK_HDMI_TX     44









#define CLK_VPOST       45









#define CLK_TGEN        46









#define CLK_DMIX        47









#define CLK_TCON        48









#define CLK_GPIO        49









#define CLK_MAILBOX     50









#define CLK_SPIND       51









#define CLK_I2C2CBUS    52









#define CLK_SEC         53









#define CLK_DVE         54









#define CLK_GPOST0      55









#define CLK_OSD0        56









#define CLK_DISP_PWM    57









#define CLK_UADBG       58









#define CLK_FIO_CTL     59









#define CLK_FPGA        60









#define CLK_L2SW        61









#define CLK_ICM         62









#define CLK_AXI_GLOBAL  63



















/* plls */









#define PLL_A           64









#define PLL_E           65









#define PLL_E_2P5       66









#define PLL_E_25        67









#define PLL_E_112P5     68









#define PLL_F           69









#define PLL_TV          70









#define PLL_TV_A        71









#define PLL_SYS         72



















#define CLK_MAX         73



















#endif