Commit 5591ce00 authored by Wojciech Dubowik's avatar Wojciech Dubowik Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2 



Define vqmmc regulator-gpio for usdhc2 with vin-supply
coming from LDO5.

Without this definition LDO5 will be powered down, disabling
SD card after bootup. This has been introduced in commit
f5aab043 ("regulator: pca9450: Fix enable register for LDO5").

Fixes: 6a57f224 ("arm64: dts: freescale: add initial support for verdin imx8m mini")
Fixes: f5aab043 ("regulator: pca9450: Fix enable register for LDO5")
Tested-by: default avatarManuel Traut <manuel.traut@mt.com>
Reviewed-by: default avatarPhilippe Schenker <philippe.schenker@impulsing.ch>
Tested-by: default avatarFrancesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: default avatarFrancesco Dolcini <francesco.dolcini@toradex.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarWojciech Dubowik <Wojciech.Dubowik@mt.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 1526a735

arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

+20 −5
Original line number Diff line number Diff line
@@ -144,6 +144,19 @@ reg_usdhc2_vmmc: regulator-usdhc2 { 
		startup-delay-us = <20000>;

	};



	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {

		compatible = "regulator-gpio";

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usdhc2_vsel>;

		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

		regulator-max-microvolt = <3300000>;

		regulator-min-microvolt = <1800000>;

		states = <1800000 0x1>,

			 <3300000 0x0>;

		regulator-name = "PMIC_USDHC_VSELECT";

		vin-supply = <&reg_nvcc_sd>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;
@@ -269,7 +282,7 @@ &gpio1 { 
			  "SODIMM_19",

			  "",

			  "",

			  "",

			  "PMIC_USDHC_VSELECT",

			  "",

			  "",

			  "",
@@ -785,6 +798,7 @@ &usdhc2 { 
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;

	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;

	vmmc-supply = <&reg_usdhc2_vmmc>;

	vqmmc-supply = <&reg_usdhc2_vqmmc>;

};



&wdog1 {
@@ -1206,13 +1220,17 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 
			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */

	};



	pinctrl_usdhc2_vsel: usdhc2vselgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x10>; /* PMIC_USDHC_VSELECT */

	};



	/*

	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the

	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.

	 */

	pinctrl_usdhc2: usdhc2grp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90>,	/* SODIMM 78 */

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90>,	/* SODIMM 74 */

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90>,	/* SODIMM 80 */
@@ -1223,7 +1241,6 @@ pinctrl_usdhc2: usdhc2grp { 


	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94>,
@@ -1234,7 +1251,6 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 


	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96>,
@@ -1246,7 +1262,6 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 
	/* Avoid backfeeding with removed card power */

	pinctrl_usdhc2_sleep: usdhc2slpgrp {

		fsl,pins =

			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,

			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,

			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,

			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,