Commit 55ae3eef authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull i2c updates from Wolfram Sang:
 "Core:

   - drivers can now use a GPIO as a side channel for SMBus Alerts using
     a generic binding

   - regular stuff like mem leak fix, Makefile maintenance...

  Host improvements and refactoring:

   - All controllers using the 'remove_new' callback have been reverted
     to use the 'remove' callback

   - Intel SCH controller underwent significant refactoring, this brings
     love and a modern look to the driver

   - PIIX4 driver refactored to enable usage by other drivers (e.g., AMD
     ASF)

   - iMX/MXC improved message handling to reduce protocol overhead:
     Refactored DMA/non-DMA read/write and bus polling mechanisms to
     achieve this.

   - ACPI documentation for PIIX4

  New host features:

   - i2c-cadence support for atomic transfers

   - Qualcomm CII support for a 32MHz serial engine clock

  Deprecated features:

   - Dropped outdated support for AMD756 S4882 and NFORCE2 S4985. If
     somebody misses this, Jean will rewrite support using the proper
     i2c mux framework.

  New hardware IDs for existing drivers:

   - Intel Panther Lake

   - S32G2/S32G3 SoCs

   - HJMC01 DesignWare ACPI HID

   - PIC64GX to Microchip Core

   - Qualcomm SDM670 to Qualcomm CCI

  New drivers:

   - AMD ASF

   - Realtek RTL I2C Controller

  at24 updates:

   - add support for the lockable page on ST M24256E"

* tag 'i2c-for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (59 commits)
  docs: i2c: piix4: Add ACPI section
  i2c: Add driver for the RTL9300 I2C controller
  i2c: qcom-cci: Remove unused struct member cci_clk_rate
  dt-bindings: i2c: Add Realtek RTL I2C Controller
  i2c: busses: Use *-y instead of *-objs in Makefile
  i2c: imx: add support for S32G2/S32G3 SoCs
  dt-bindings: i2c: imx: add SoC specific compatible strings for S32G
  i2c: qcom-cci: Remove the unused variable cci_clk_rate
  i2c: Drop legacy muxing pseudo-drivers
  i2c: imx: prevent rescheduling in non dma mode
  i2c: imx: separate atomic, dma and non-dma use case
  i2c: imx: do not poll for bus busy in single master mode
  i2c: designware: Add a new ACPI HID for HJMC01 I2C controller
  i2c: qcom-geni: Keep comment why interrupts start disabled
  dt-bindings: i2c: microchip: corei2c: Add PIC64GX as compatible with driver
  i2c: designware: constify abort_sources
  i2c: Switch back to struct platform_driver::remove()
  i2c: qcom-geni: Support systems with 32MHz serial engine clock
  i2c: qcom-cci: Stop complaining about DT set clock rate
  dt-bindings: i2c: qcom-cci: Document SDM670 compatible
  ...
parents 341d041d 1b307329
Loading
Loading
Loading
Loading
+2 −0
Original line number Diff line number Diff line
@@ -141,6 +141,8 @@ properties:
          - const: microchip,24aa025e48
      - items:
          - const: microchip,24aa025e64
      - items:
          - const: st,24256e-wl
      - pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st

  label:
+4 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties:
      - const: fsl,imx1-i2c
      - const: fsl,imx21-i2c
      - const: fsl,vf610-i2c
      - const: nxp,s32g2-i2c
      - items:
          - enum:
              - fsl,ls1012a-i2c
@@ -54,6 +55,9 @@ properties:
              - fsl,imx8mn-i2c
              - fsl,imx8mp-i2c
          - const: fsl,imx21-i2c
      - items:
          - const: nxp,s32g3-i2c
          - const: nxp,s32g2-i2c

  reg:
    maxItems: 1
+3 −1
Original line number Diff line number Diff line
@@ -16,7 +16,9 @@ properties:
  compatible:
    oneOf:
      - items:
          - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
          - enum:
              - microchip,pic64gx-i2c
              - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
          - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
      - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core

+19 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties:
          - enum:
              - qcom,sc7280-cci
              - qcom,sc8280xp-cci
              - qcom,sdm670-cci
              - qcom,sdm845-cci
              - qcom,sm6350-cci
              - qcom,sm8250-cci
@@ -139,6 +140,24 @@ allOf:
            - const: cci
            - const: camss_ahb

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm670-cci
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: camnoc_axi
            - const: soc_ahb
            - const: cpas_ahb
            - const: cci

  - if:
      properties:
        compatible:
+69 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/realtek,rtl9301-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek RTL I2C Controller

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

description:
  The RTL9300 SoC has two I2C controllers. Each of these has an SCL line (which
  if not-used for SCL can be a GPIO). There are 8 common SDA lines that can be
  assigned to either I2C controller.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - realtek,rtl9302b-i2c
              - realtek,rtl9302c-i2c
              - realtek,rtl9303-i2c
          - const: realtek,rtl9301-i2c
      - const: realtek,rtl9301-i2c

  reg:
    description: Register offset and size this I2C controller.

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  '^i2c@[0-7]$':
    $ref: /schemas/i2c/i2c-controller.yaml
    unevaluatedProperties: false

    properties:
      reg:
        description: The SDA pin associated with the I2C bus.
        maxItems: 1

    required:
      - reg

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c@36c {
      compatible = "realtek,rtl9301-i2c";
      reg = <0x36c 0x14>;
      #address-cells = <1>;
      #size-cells = <0>;

      i2c@2 {
        reg = <2>;
        #address-cells = <1>;
        #size-cells = <0>;
      };
    };
Loading