Commit 55b19abb authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe: Consolidate workaround entries for Wa_14019877138 



Wa_14019877138 applies to all graphics versions from 12.55 through 20.04
(inclusive) that have a render engine.  Consolidate the RTP entries into
a single range-based entry.

Note that the DG2 entry for this workaround was missing an
ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation.

Reviewed-by: default avatarShuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-16-b12005a05af6@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 7b6f615d

drivers/gpu/drm/xe/xe_wa.c

+4 −16
Original line number Diff line number Diff line
@@ -648,6 +648,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, 2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},



	/* DG1 */
@@ -684,10 +688,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(PLATFORM(DG2)),

	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(PLATFORM(DG2)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},



	/* PVC */
@@ -705,10 +705,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274)),

	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},



	/* Xe2_LPG */
@@ -716,10 +712,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},

	{ XE_RTP_NAME("14019988906"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
@@ -769,10 +761,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))

	},

	{ XE_RTP_NAME("14019877138"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},

	{ XE_RTP_NAME("14021490052"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(FF_MODE,