Unverified Commit 5621a7bc authored by David Lechner's avatar David Lechner Committed by Mark Brown
Browse files

spi: add multi_lane_mode field to struct spi_transfer 



Add a new multi_lane_mode field to struct spi_transfer to allow
peripherals that support multiple SPI lanes to be used with a single
SPI controller.

This requires both the peripheral and the controller to have multiple
serializers connected to separate data lanes. It could also be used with
a single controller and multiple peripherals that are functioning as a
single logical device (similar to parallel memories).

Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Acked-by: default avatarMarcelo Schmitt <marcelo.schmitt@analog.com>
Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: default avatarDavid Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-4-12af183c06eb@baylibre.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 002d561f

include/linux/spi/spi.h

+8 −0
Original line number Diff line number Diff line
@@ -981,6 +981,8 @@ struct spi_res { 
 *      (SPI_NBITS_SINGLE) is used.

 * @rx_nbits: number of bits used for reading. If 0 the default

 *      (SPI_NBITS_SINGLE) is used.

 * @multi_lane_mode: How to serialize data on multiple lanes. One of the

 *      SPI_MULTI_LANE_MODE_* values.

 * @len: size of rx and tx buffers (in bytes)

 * @speed_hz: Select a speed other than the device default for this

 *      transfer. If 0 the default (from @spi_device) is used.
@@ -1117,6 +1119,12 @@ struct spi_transfer { 
	unsigned	cs_change:1;

	unsigned	tx_nbits:4;

	unsigned	rx_nbits:4;



#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */

#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */

#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */

	unsigned	multi_lane_mode: 2;



	unsigned	timestamped:1;

	bool		dtr_mode;

#define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */