Commit 563e1feb authored by Faisal Latif's avatar Faisal Latif Committed by Leon Romanovsky
Browse files

RDMA/irdma: Add SRQ support 



Implement verb API and UAPI changes to support SRQ functionality in GEN3
devices.

Signed-off-by: default avatarFaisal Latif <faisal.latif@intel.com>
Signed-off-by: default avatarTatyana Nikolova <tatyana.e.nikolova@intel.com>
Link: https://patch.msgid.link/20250827152545.2056-13-tatyana.e.nikolova@intel.com


Tested-by: default avatarJacob Moroni <jmoroni@google.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 9a1d6878

drivers/infiniband/hw/irdma/ctrl.c

+234 −2
Original line number Diff line number Diff line
@@ -412,7 +412,8 @@ int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info) 
	pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt;



	if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) ||

	    (info->virtual_map && info->rq_pa >= pble_obj_cnt))

	    (!info->qp_uk_init_info.srq_uk &&

	     info->virtual_map && info->rq_pa >= pble_obj_cnt))

		return -EINVAL;



	qp->llp_stream_handle = (void *)(-1);
@@ -446,6 +447,208 @@ int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info) 
	return 0;

}



/**

 * irdma_sc_srq_init - init sc_srq structure

 * @srq: srq sc struct

 * @info: parameters for srq init

 */

int irdma_sc_srq_init(struct irdma_sc_srq *srq,

		      struct irdma_srq_init_info *info)

{

	u32 srq_size_quanta;

	int ret_code;



	ret_code = irdma_uk_srq_init(&srq->srq_uk, &info->srq_uk_init_info);

	if (ret_code)

		return ret_code;



	srq->dev = info->pd->dev;

	srq->pd = info->pd;

	srq->vsi = info->vsi;

	srq->srq_pa = info->srq_pa;

	srq->first_pm_pbl_idx = info->first_pm_pbl_idx;

	srq->pasid = info->pasid;

	srq->pasid_valid = info->pasid_valid;

	srq->srq_limit = info->srq_limit;

	srq->leaf_pbl_size = info->leaf_pbl_size;

	srq->virtual_map = info->virtual_map;

	srq->tph_en = info->tph_en;

	srq->arm_limit_event = info->arm_limit_event;

	srq->tph_val = info->tph_value;

	srq->shadow_area_pa = info->shadow_area_pa;



	/* Smallest SRQ size is 256B i.e. 8 quanta */

	srq_size_quanta = max((u32)IRDMA_SRQ_MIN_QUANTA,

			      srq->srq_uk.srq_size *

			      srq->srq_uk.wqe_size_multiplier);

	srq->hw_srq_size = irdma_get_encoded_wqe_size(srq_size_quanta,

						      IRDMA_QUEUE_TYPE_SRQ);



	return 0;

}



/**

 * irdma_sc_srq_create - send srq create CQP WQE

 * @srq: srq sc struct

 * @scratch: u64 saved to be used during cqp completion

 * @post_sq: flag for cqp db to ring

 */

static int irdma_sc_srq_create(struct irdma_sc_srq *srq, u64 scratch,

			       bool post_sq)

{

	struct irdma_sc_cqp *cqp;

	__le64 *wqe;

	u64 hdr;



	cqp = srq->pd->dev->cqp;

	if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id ||

	    srq->srq_uk.srq_id >

	    (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1))

		return -EINVAL;



	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

	if (!wqe)

		return -ENOMEM;



	set_64bit_val(wqe, 0,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, srq->srq_limit) |

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) |

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size));

	set_64bit_val(wqe, 8, (uintptr_t)srq);

	set_64bit_val(wqe, 16,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id));

	set_64bit_val(wqe, 32,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR,

				 srq->srq_pa >>

				 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S));

	set_64bit_val(wqe, 40,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR,

				 srq->shadow_area_pa >>

				 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S));

	set_64bit_val(wqe, 48,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX,

				 srq->first_pm_pbl_idx));



	hdr = srq->srq_uk.srq_id |

	      FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_SRQ) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT,

			 srq->arm_limit_event) |

	      FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);



	dma_wmb(); /* make sure WQE is written before valid bit is set */



	set_64bit_val(wqe, 24, hdr);



	print_hex_dump_debug("WQE: SRQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8,

			     wqe, IRDMA_CQP_WQE_SIZE * 8, false);

	if (post_sq)

		irdma_sc_cqp_post_sq(cqp);



	return 0;

}



/**

 * irdma_sc_srq_modify - send modify_srq CQP WQE

 * @srq: srq sc struct

 * @info: parameters for srq modification

 * @scratch: u64 saved to be used during cqp completion

 * @post_sq: flag for cqp db to ring

 */

static int irdma_sc_srq_modify(struct irdma_sc_srq *srq,

			       struct irdma_modify_srq_info *info, u64 scratch,

			       bool post_sq)

{

	struct irdma_sc_cqp *cqp;

	__le64 *wqe;

	u64 hdr;



	cqp = srq->dev->cqp;

	if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id ||

	    srq->srq_uk.srq_id >

	    (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1))

		return -EINVAL;



	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

	if (!wqe)

		return -ENOMEM;



	set_64bit_val(wqe, 0,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, info->srq_limit) |

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) |

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size));

	set_64bit_val(wqe, 8,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQCTX, srq->srq_uk.srq_id));

	set_64bit_val(wqe, 16,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id));

	set_64bit_val(wqe, 32,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR,

				 srq->srq_pa >>

				 IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S));

	set_64bit_val(wqe, 40,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR,

				 srq->shadow_area_pa >>

				 IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S));

	set_64bit_val(wqe, 48,

		      FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX,

				 srq->first_pm_pbl_idx));



	hdr = srq->srq_uk.srq_id |

	      FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_SRQ) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) |

	      FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT,

			 info->arm_limit_event) |

	      FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	dma_wmb(); /* make sure WQE is written before valid bit is set */



	set_64bit_val(wqe, 24, hdr);



	print_hex_dump_debug("WQE: SRQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8,

			     wqe, IRDMA_CQP_WQE_SIZE * 8, false);

	if (post_sq)

		irdma_sc_cqp_post_sq(cqp);



	return 0;

}



/**

 * irdma_sc_srq_destroy - send srq_destroy CQP WQE

 * @srq: srq sc struct

 * @scratch: u64 saved to be used during cqp completion

 * @post_sq: flag for cqp db to ring

 */

static int irdma_sc_srq_destroy(struct irdma_sc_srq *srq, u64 scratch,

				bool post_sq)

{

	struct irdma_sc_cqp *cqp;

	__le64 *wqe;

	u64 hdr;



	cqp = srq->dev->cqp;



	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);

	if (!wqe)

		return -ENOMEM;



	set_64bit_val(wqe, 8, (uintptr_t)srq);



	hdr = srq->srq_uk.srq_id |

	      FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_SRQ) |

	      FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	dma_wmb(); /* make sure WQE is written before valid bit is set */



	set_64bit_val(wqe, 24, hdr);



	print_hex_dump_debug("WQE: SRQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16,

			     8, wqe, IRDMA_CQP_WQE_SIZE * 8, false);

	if (post_sq)

		irdma_sc_cqp_post_sq(cqp);



	return 0;

}



/**

 * irdma_sc_qp_create - create qp

 * @qp: sc qp
@@ -837,6 +1040,7 @@ static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, 
	      FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) |

	      FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) |

	      FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) |

	      FIELD_PREP(IRDMAQPC_USE_SRQ, !qp->qp_uk.srq_uk ? 0 : 1) |

	      FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag);

	set_64bit_val(qp_ctx, 0, qw0);

	set_64bit_val(qp_ctx, 8, qp->sq_pa);
@@ -921,6 +1125,9 @@ static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, 
		      FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0]));

	set_64bit_val(qp_ctx, 200,

		      FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) |

		      FIELD_PREP(IRDMAQPC_SRQ_ID,

				 !qp->qp_uk.srq_uk ?

					0 : qp->qp_uk.srq_uk->srq_id) |

		      FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low));

	set_64bit_val(qp_ctx, 208, roce_info->pd_id |

		      FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) |
@@ -2219,6 +2426,14 @@ u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) 
{

	u8 encoded_size = 0;



	if (queue_type == IRDMA_QUEUE_TYPE_SRQ) {

		/* Smallest SRQ size is 256B (8 quanta) that gets

		 * encoded to 0.

		 */

		encoded_size = ilog2(wqsize) - 3;



		return encoded_size;

	}

	/* cqp sq's hw coded value starts from 1 for size of 4

	 * while it starts from 0 for qp' wq's.

	 */
@@ -4585,7 +4800,7 @@ int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, 
	case IRDMA_AE_SRQ_LIMIT:

		info->srq = true;

		/* [63:6] from CMPL_CTXT, [5:0] from WQDESCIDX. */

		info->compl_ctx = compl_ctx | info->wqe_idx;

		info->compl_ctx = compl_ctx;

		ae_src = IRDMA_AE_SOURCE_RSVD;

		break;

	case IRDMA_AE_PRIV_OPERATION_DENIED:
@@ -6161,6 +6376,22 @@ static int irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, 
						   &pcmdinfo->in.u.mc_modify.info,

						   pcmdinfo->in.u.mc_modify.scratch);

		break;

	case IRDMA_OP_SRQ_CREATE:

		status = irdma_sc_srq_create(pcmdinfo->in.u.srq_create.srq,

					     pcmdinfo->in.u.srq_create.scratch,

					     pcmdinfo->post_sq);

		break;

	case IRDMA_OP_SRQ_MODIFY:

		status = irdma_sc_srq_modify(pcmdinfo->in.u.srq_modify.srq,

					     &pcmdinfo->in.u.srq_modify.info,

					     pcmdinfo->in.u.srq_modify.scratch,

					     pcmdinfo->post_sq);

		break;

	case IRDMA_OP_SRQ_DESTROY:

		status = irdma_sc_srq_destroy(pcmdinfo->in.u.srq_destroy.srq,

					      pcmdinfo->in.u.srq_destroy.scratch,

					      pcmdinfo->post_sq);

		break;

	default:

		status = -EOPNOTSUPP;

		break;
@@ -6318,6 +6549,7 @@ int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev, 
	dev->protocol_used = info->protocol_used;

	/* Setup the hardware limits, hmc may limit further */

	dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID;

	dev->hw_attrs.min_hw_srq_id = IRDMA_MIN_IW_SRQ_ID;

	dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES;

	if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3)

		dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES_GEN_3;

drivers/infiniband/hw/irdma/defs.h

+35 −1
Original line number Diff line number Diff line
@@ -140,7 +140,11 @@ enum irdma_protocol_used { 
#define IRDMA_QP_SW_MAX_RQ_QUANTA	32768

#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \

	((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))

#define IRDMA_SRQ_MIN_QUANTA 8

#define IRDMA_SRQ_MAX_QUANTA 262144

#define IRDMA_MAX_SRQ_WRS \

	((IRDMA_SRQ_MAX_QUANTA - IRDMA_RQ_RSVD) / IRDMA_MAX_QUANTA_PER_WR)



#define IRDMAQP_TERM_SEND_TERM_AND_FIN		0

#define IRDMAQP_TERM_SEND_TERM_ONLY		1

#define IRDMAQP_TERM_SEND_FIN_ONLY		2
@@ -236,9 +240,12 @@ enum irdma_cqp_op_type { 
	IRDMA_OP_ADD_LOCAL_MAC_ENTRY		= 46,

	IRDMA_OP_DELETE_LOCAL_MAC_ENTRY		= 47,

	IRDMA_OP_CQ_MODIFY			= 48,

	IRDMA_OP_SRQ_CREATE			= 49,

	IRDMA_OP_SRQ_MODIFY			= 50,

	IRDMA_OP_SRQ_DESTROY			= 51,



	/* Must be last entry*/

	IRDMA_MAX_CQP_OPS			= 49,

	IRDMA_MAX_CQP_OPS			= 52,

};



/* CQP SQ WQES */
@@ -248,6 +255,9 @@ enum irdma_cqp_op_type { 
#define IRDMA_CQP_OP_CREATE_CQ				0x03

#define IRDMA_CQP_OP_MODIFY_CQ				0x04

#define IRDMA_CQP_OP_DESTROY_CQ				0x05

#define IRDMA_CQP_OP_CREATE_SRQ				0x06

#define IRDMA_CQP_OP_MODIFY_SRQ				0x07

#define IRDMA_CQP_OP_DESTROY_SRQ			0x08

#define IRDMA_CQP_OP_ALLOC_STAG				0x09

#define IRDMA_CQP_OP_REG_MR				0x0a

#define IRDMA_CQP_OP_QUERY_STAG				0x0b
@@ -519,6 +529,7 @@ enum irdma_cqp_op_type { 
#define IRDMA_CQ_ERROR BIT_ULL(55)

#define IRDMA_CQ_SQ BIT_ULL(62)



#define IRDMA_CQ_SRQ BIT_ULL(52)

#define IRDMA_CQ_VALID BIT_ULL(63)

#define IRDMA_CQ_IMMVALID BIT_ULL(62)

#define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
@@ -628,6 +639,24 @@ enum irdma_cqp_op_type { 


#define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX



#define IRDMA_CQPSQ_SRQ_RQSIZE GENMASK_ULL(3, 0)

#define IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE GENMASK_ULL(5, 4)

#define IRDMA_CQPSQ_SRQ_SRQ_LIMIT GENMASK_ULL(43, 32)

#define IRDMA_CQPSQ_SRQ_SRQCTX GENMASK_ULL(63, 6)

#define IRDMA_CQPSQ_SRQ_PD_ID GENMASK_ULL(39, 16)

#define IRDMA_CQPSQ_SRQ_SRQ_ID GENMASK_ULL(15, 0)

#define IRDMA_CQPSQ_SRQ_OP GENMASK_ULL(37, 32)

#define IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE GENMASK_ULL(45, 44)

#define IRDMA_CQPSQ_SRQ_VIRTMAP BIT_ULL(47)

#define IRDMA_CQPSQ_SRQ_TPH_EN BIT_ULL(60)

#define IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT BIT_ULL(61)

#define IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX GENMASK_ULL(27, 0)

#define IRDMA_CQPSQ_SRQ_TPH_VALUE GENMASK_ULL(7, 0)

#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S 8

#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR GENMASK_ULL(63, 8)

#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S 6

#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR GENMASK_ULL(63, 6)



#define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)

#define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)

#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
@@ -779,6 +808,11 @@ enum irdma_cqp_op_type { 
#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)

#define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)



#define IRDMAQPC_USE_SRQ BIT_ULL(10)

#define IRDMAQPC_SRQ_ID GENMASK_ULL(15, 0)

#define IRDMAQPC_PASID GENMASK_ULL(19, 0)

#define IRDMAQPC_PASID_VALID BIT_ULL(11)



#define IRDMAQPC_ECN_EN BIT_ULL(14)

#define IRDMAQPC_DROPOOOSEG BIT_ULL(15)

#define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)

drivers/infiniband/hw/irdma/hw.c

+19 −2
Original line number Diff line number Diff line
@@ -269,6 +269,7 @@ static void irdma_process_aeq(struct irdma_pci_f *rf) 
	struct irdma_sc_qp *qp = NULL;

	struct irdma_qp_host_ctx_info *ctx_info = NULL;

	struct irdma_device *iwdev = rf->iwdev;

	struct irdma_sc_srq *srq;

	unsigned long flags;



	u32 aeqcnt = 0;
@@ -320,6 +321,9 @@ static void irdma_process_aeq(struct irdma_pci_f *rf) 
				iwqp->last_aeq = info->ae_id;

			spin_unlock_irqrestore(&iwqp->lock, flags);

			ctx_info = &iwqp->ctx_info;

		} else if (info->srq) {

			if (info->ae_id != IRDMA_AE_SRQ_LIMIT)

				continue;

		} else {

			if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR &&

			    info->ae_id != IRDMA_AE_CQP_DEFERRED_COMPLETE)
@@ -417,6 +421,12 @@ static void irdma_process_aeq(struct irdma_pci_f *rf) 
			}

			irdma_cq_rem_ref(&iwcq->ibcq);

			break;

		case IRDMA_AE_SRQ_LIMIT:

			srq = (struct irdma_sc_srq *)(uintptr_t)info->compl_ctx;

			irdma_srq_event(srq);

			break;

		case IRDMA_AE_SRQ_CATASTROPHIC_ERROR:

			break;

		case IRDMA_AE_CQP_DEFERRED_COMPLETE:

			/* Remove completed CQP requests from pending list

			 * and notify about those CQP ops completion.
@@ -1840,6 +1850,8 @@ static void irdma_get_used_rsrc(struct irdma_device *iwdev) 
						 iwdev->rf->max_qp);

	iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,

						  iwdev->rf->max_cq);

	iwdev->rf->used_srqs = find_first_zero_bit(iwdev->rf->allocated_srqs,

						   iwdev->rf->max_srq);

	iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,

						 iwdev->rf->max_mr);

}
@@ -2056,7 +2068,8 @@ static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) 
	rf->allocated_qps = (void *)(rf->mem_rsrc +

		   (sizeof(struct irdma_arp_entry) * rf->arp_table_size));

	rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];

	rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];

	rf->allocated_srqs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];

	rf->allocated_mrs = &rf->allocated_srqs[BITS_TO_LONGS(rf->max_srq)];

	rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];

	rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];

	rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
@@ -2084,12 +2097,14 @@ static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 
	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_srq);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);

	rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);

	rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;

	rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq;

	rsrc_size += sizeof(struct irdma_srq **) * rf->max_srq;



	return rsrc_size;

}
@@ -2117,6 +2132,7 @@ u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 
	rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;

	rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;

	rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;

	rf->max_srq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt;

	rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;

	rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;

	rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
@@ -2136,6 +2152,7 @@ u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 
	set_bit(0, rf->allocated_mrs);

	set_bit(0, rf->allocated_qps);

	set_bit(0, rf->allocated_cqs);

	set_bit(0, rf->allocated_srqs);

	set_bit(0, rf->allocated_pds);

	set_bit(0, rf->allocated_arps);

	set_bit(0, rf->allocated_ahs);

drivers/infiniband/hw/irdma/irdma.h

+1 −0
Original line number Diff line number Diff line
@@ -162,6 +162,7 @@ struct irdma_hw_attrs { 
	u32 max_done_count;

	u32 max_sleep_count;

	u32 max_cqp_compl_wait_time_ms;

	u32 min_hw_srq_id;

	u16 max_stat_inst;

	u16 max_stat_idx;

};

drivers/infiniband/hw/irdma/main.h

+11 −1
Original line number Diff line number Diff line
@@ -274,6 +274,8 @@ struct irdma_pci_f { 
	u32 max_mr;

	u32 max_qp;

	u32 max_cq;

	u32 max_srq;

	u32 next_srq;

	u32 max_ah;

	u32 next_ah;

	u32 max_mcg;
@@ -287,6 +289,7 @@ struct irdma_pci_f { 
	u32 mr_stagmask;

	u32 used_pds;

	u32 used_cqs;

	u32 used_srqs;

	u32 used_mrs;

	u32 used_qps;

	u32 arp_table_size;
@@ -298,6 +301,7 @@ struct irdma_pci_f { 
	unsigned long *allocated_ws_nodes;

	unsigned long *allocated_qps;

	unsigned long *allocated_cqs;

	unsigned long *allocated_srqs;

	unsigned long *allocated_mrs;

	unsigned long *allocated_pds;

	unsigned long *allocated_mcgs;
@@ -421,6 +425,11 @@ static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev) 
	return container_of(dev, struct irdma_pci_f, sc_dev);

}



static inline struct irdma_srq *to_iwsrq(struct ib_srq *ibsrq)

{

	return container_of(ibsrq, struct irdma_srq, ibsrq);

}



/**

 * irdma_alloc_resource - allocate a resource

 * @iwdev: device pointer
@@ -516,7 +525,8 @@ int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, 
void irdma_cq_add_ref(struct ib_cq *ibcq);

void irdma_cq_rem_ref(struct ib_cq *ibcq);

void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);



void irdma_srq_event(struct irdma_sc_srq *srq);

void irdma_srq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_srq *srq);

void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf);

int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,

		       struct irdma_modify_qp_info *info, bool wait);