Commit 565e4684 authored by Jonathan Neuschäfer's avatar Jonathan Neuschäfer Committed by Ulf Hansson
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dt-bindings: mmc: fsl-imx-esdhc: Improve grammar and fix a typo

parent 418f7c2d
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+2 −2
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ properties:
      Specify the number of delay cells for override mode.
      This is used to set the clock delay for DLL(Delay Line) on override mode
      to select a proper data sampling window in case the clock quality is not good
      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
      because the signal path is too long on the board. Please refer to eSDHC/uSDHC
      chapter, DLL (Delay Line) section in RM for details.
    default: 0

@@ -136,7 +136,7 @@ properties:
      Specify the increasing delay cell steps in tuning procedure.
      The uSDHC use one delay cell as default increasing step to do tuning process.
      This property allows user to change the tuning step to more than one delay
      cells which is useful for some special boards or cards when the default
      cell which is useful for some special boards or cards when the default
      tuning step can't find the proper delay window within limited tuning retries.
    default: 0