Commit 56b70bf9 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-misc-next-2024-11-08' of...

Merge tag 'drm-misc-next-2024-11-08' of https://gitlab.freedesktop.org/drm/misc/kernel

 into drm-next

drm-misc-next for v6.13:

UAPI Changes:
- Add 1X7X5 media-bus formats.

Cross-subsystem Changes:
- Maintainer updates for VKMS and IT6263.
- Add media-bus-fmt for MEDIA_BUS_FMT_RGB101010_1X7X5_*.
- Add IT6263 DT bindings and driver.

Core Changes:
- Add ABGR210101010 support to panic handler.
- Use ATOMIC64_INIT in drm_file.c
- Improve scheduler teardown documentation.

Driver Changes:
- Make mediatek compile on ARM again.
- Add missing drm/drm_bridge.h header include, already in drm-next.
- Small fixes and cleanups to vkms, bridge/it6505, panfrost, panthor.
- Add panic support to nouveau for nv50+.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/344afe41-d27b-408a-8542-bfecfd3555f6@linux.intel.com
parents 35a6e15a baf4afc5
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ITE IT6263 LVDS to HDMI converter

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) LVDS
  to HDMI converter.  Combined with LVDS receiver and HDMI 1.4a transmitter,
  the IT6263 supports LVDS input and HDMI 1.4 output by conversion function.
  The built-in LVDS receiver can support single-link and dual-link LVDS inputs,
  and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, HDCP
  1.2 and backward compatible with DVI 1.0 specification.

  The IT6263 also encodes and transmits up to 8 channels of I2S digital audio,
  with sampling rate up to 192KHz and sample size up to 24 bits. In addition,
  an S/PDIF input port takes in compressed audio of up to 192KHz frame rate.

  The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3 is
  provided by the IT6263 in two interfaces: the four I2S input ports or the
  S/PDIF input port.  With both interfaces the highest possible HBR frame rate
  is supported at up to 768KHz.

allOf:
  - $ref: /schemas/display/lvds-dual-ports.yaml#

properties:
  compatible:
    const: ite,it6263

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description: audio master clock

  clock-names:
    const: mclk

  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - jeida-30
      - vesa-24
      - vesa-30

  reset-gpios:
    maxItems: 1

  ivdd-supply:
    description: 1.8V digital logic power

  ovdd-supply:
    description: 3.3V I/O pin power

  txavcc18-supply:
    description: 1.8V HDMI analog frontend power

  txavcc33-supply:
    description: 3.3V HDMI analog frontend power

  pvcc1-supply:
    description: 1.8V HDMI frontend core PLL power

  pvcc2-supply:
    description: 1.8V HDMI frontend filter PLL power

  avcc-supply:
    description: 3.3V LVDS frontend power

  anvdd-supply:
    description: 1.8V LVDS frontend analog power

  apvdd-supply:
    description: 1.8V LVDS frontend PLL power

  "#sound-dai-cells":
    const: 0

  ite,i2s-audio-fifo-sources:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    items:
      enum: [0, 1, 2, 3]
    description:
      Each array element indicates the pin number of an I2S serial data input
      line which is connected to an audio FIFO, from audio FIFO0 to FIFO3.

  ite,rl-channel-swap-audio-sources:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    uniqueItems: true
    items:
      enum: [0, 1, 2, 3]
    description:
      Each array element indicates an audio source whose right channel and left
      channel are swapped by this converter. For I2S, the element is the pin
      number of an I2S serial data input line. For S/PDIF, the element is always
      0.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0: true

      port@1:
        oneOf:
          - required: [dual-lvds-odd-pixels]
          - required: [dual-lvds-even-pixels]

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: video port for the HDMI output

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: sound input port

    required:
      - port@0
      - port@2

required:
  - compatible
  - reg
  - data-mapping
  - ivdd-supply
  - ovdd-supply
  - txavcc18-supply
  - txavcc33-supply
  - pvcc1-supply
  - pvcc2-supply
  - avcc-supply
  - anvdd-supply
  - apvdd-supply

unevaluatedProperties: false

examples:
  - |
    /* single-link LVDS input */
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        hdmi@4c {
            compatible = "ite,it6263";
            reg = <0x4c>;
            data-mapping = "jeida-24";
            reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
            ivdd-supply = <&reg_buck5>;
            ovdd-supply = <&reg_vext_3v3>;
            txavcc18-supply = <&reg_buck5>;
            txavcc33-supply = <&reg_vext_3v3>;
            pvcc1-supply = <&reg_buck5>;
            pvcc2-supply = <&reg_buck5>;
            avcc-supply = <&reg_vext_3v3>;
            anvdd-supply = <&reg_buck5>;
            apvdd-supply = <&reg_buck5>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    it6263_lvds_link1: endpoint {
                        remote-endpoint = <&ldb_lvds_ch0>;
                    };
                };

                port@2 {
                    reg = <2>;

                    it6263_out: endpoint {
                        remote-endpoint = <&hdmi_in>;
                    };
                };
            };
        };
    };

  - |
    /* dual-link LVDS input */
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        hdmi@4c {
            compatible = "ite,it6263";
            reg = <0x4c>;
            data-mapping = "jeida-24";
            reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
            ivdd-supply = <&reg_buck5>;
            ovdd-supply = <&reg_vext_3v3>;
            txavcc18-supply = <&reg_buck5>;
            txavcc33-supply = <&reg_vext_3v3>;
            pvcc1-supply = <&reg_buck5>;
            pvcc2-supply = <&reg_buck5>;
            avcc-supply = <&reg_vext_3v3>;
            anvdd-supply = <&reg_buck5>;
            apvdd-supply = <&reg_buck5>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dual-lvds-odd-pixels;

                    it6263_lvds_link1_dual: endpoint {
                        remote-endpoint = <&ldb_lvds_ch0>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dual-lvds-even-pixels;

                    it6263_lvds_link2_dual: endpoint {
                        remote-endpoint = <&ldb_lvds_ch1>;
                    };
                };

                port@2 {
                    reg = <2>;

                    it6263_out_dual: endpoint {
                        remote-endpoint = <&hdmi_in>;
                    };
                };
            };
        };
    };
+31 −0
Original line number Diff line number Diff line
@@ -26,12 +26,17 @@ description: |
  Device compatible with those specifications have been marketed under the
  FPD-Link and FlatLink brands.

  This bindings also supports 30-bit data mapping compatible with JEIDA and
  VESA.

properties:
  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - jeida-30
      - vesa-24
      - vesa-30
    description: |
      The color signals mapping order.

@@ -60,6 +65,19 @@ properties:
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data
        are transferred as follows on 5 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__><
      DATA1     ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__><
      DATA3     ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__><
      DATA4     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
        Data are transferred as follows on 4 LVDS lanes.

@@ -72,6 +90,19 @@ properties:
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><

      - "vesa-30" - 30-bit data mapping compatible with VESA. Data are
        transferred as follows on 5 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
      DATA4     ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__><

      Control signals are mapped as follows.

      CTL0: HSync
+63 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/lvds-dual-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Dual-link LVDS Display Common Properties

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  Common properties for LVDS displays with dual LVDS links. Extend LVDS display
  common properties defined in lvds.yaml.

  Dual-link LVDS displays receive odd pixels and even pixels separately from
  the dual LVDS links. One link receives odd pixels and the other receives
  even pixels. Some of those displays may also use only one LVDS link to
  receive all pixels, being odd and even agnostic.

allOf:
  - $ref: lvds.yaml#

properties:
  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    patternProperties:
      '^port@[01]$':
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
          port@0 represents the first LVDS input link.
          port@1 represents the second LVDS input link.

        properties:
          dual-lvds-odd-pixels:
            type: boolean
            description: LVDS input link for odd pixels

          dual-lvds-even-pixels:
            type: boolean
            description: LVDS input link for even pixels

        oneOf:
          - required: [dual-lvds-odd-pixels]
          - required: [dual-lvds-even-pixels]
          - properties:
              dual-lvds-odd-pixels: false
              dual-lvds-even-pixels: false

    anyOf:
      - required:
          - port@0
      - required:
          - port@1

required:
  - ports

additionalProperties: true

...
+1 −13
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@@ -20,6 +20,7 @@ description: |
  dual-lvds-odd-pixels or dual-lvds-even-pixels).

allOf:
  - $ref: /schemas/display/lvds-dual-ports.yaml#
  - $ref: panel-common.yaml#

properties:
@@ -44,22 +45,10 @@ properties:

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The sink for odd pixels.
        properties:
          dual-lvds-odd-pixels: true

        required:
          - dual-lvds-odd-pixels

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The sink for even pixels.
        properties:
          dual-lvds-even-pixels: true

        required:
          - dual-lvds-even-pixels

@@ -75,7 +64,6 @@ required:
  - height-mm
  - data-mapping
  - panel-timing
  - ports

examples:
  - |+
+1 −19
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ description: |
  If the panel is more advanced a dedicated binding file is required.

allOf:
  - $ref: /schemas/display/lvds-dual-ports.yaml#
  - $ref: panel-common.yaml#

properties:
@@ -55,28 +56,10 @@ properties:

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The first sink port.

        properties:
          dual-lvds-odd-pixels:
            type: boolean
            description: The first sink port for odd pixels.

        required:
          - dual-lvds-odd-pixels

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The second sink port.

        properties:
          dual-lvds-even-pixels:
            type: boolean
            description: The second sink port for even pixels.

        required:
          - dual-lvds-even-pixels

@@ -88,7 +71,6 @@ unevaluatedProperties: false

required:
  - compatible
  - ports
  - power-supply

examples:
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